RTL verification

Concept

RTL verification, in the provided processor-verification evidence, is verification of a processor at the Register-Transfer Level. It is described as crucial because processor bugs can lengthen design cycles and create significant follow-up costs. Simulation-based RTL verification commonly depends on strong stimulus generation: one RISC-V cross-level approach feeds generated instruction streams to both an RTL core and an Instruction Set Simulator reference model, comparing results after each executed instruction. RISC-V verification tooling such as riscv-dv and its riscv_asm_program_gen class supports this workflow by generating randomized assembly programs and related program sections for RISC-V IP verification.

First seen 5/26/2026

Last seen 5/30/2026

Evidence 4 chunks

Wiki v2

WIKI

Overview

RTL verification is discussed in the evidence as verification of a processor at the Register-Transfer Level (RTL). Extensive RTL verification is described as crucial because processor bugs can lead to longer design cycles and significant follow-up costs. [C1]

Simulation-based methods are described as prevalent in the verification domain because of their ease of use and scalability. In processor RTL verification, this makes stimulus generation and comparison against a reference behavior central parts of the verification workflow. [C1]

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simulation-based verification uses → 95% 2e

RTL verification predominantly uses simulation-based methods.

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← uses 100% 2e

The paper focuses on RTL verification of RISC-V processors.

riscv-dv ← evaluates 2e

riscv-dv is used to perform RTL verification of RISC-V IP.

riscv_asm_program_gen ← uses 1e

riscv_asm_program_gen generates programs used for RTL verification of RISC-V IP.

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riscv-dv EVALUATES Extracted graph relationship

riscv_asm_program_gen USES Extracted graph relationship

CITATIONS

7 sources

7 citations — click to expand

[1] C1: Processor RTL verification is crucial to avoid bugs that can lengthen design cycles and create follow-up costs, and simulation-based methods are prevalent because of ease of use and scalability. [PDF] Efficient Cross-Level Testing for Processor Verification: A RISC-V ...

[2] C2: The RISC-V cross-level approach generates an endless instruction stream, uses an ISS as the reference model for the RTL core, feeds the stream to both ISS and RTL, and compares results after each executed instruction. [PDF] Efficient Cross-Level Testing for Processor Verification: A RISC-V ...

[3] C3: Official hand-written RISC-V test suites cover basic sanity checks and some corner cases across extensions, but are described as having very limited coverage and being unsuitable for continuous testing. [PDF] Efficient Cross-Level Testing for Processor Verification: A RISC-V ...

[4] C4: CHIPS Alliance developed riscv-dv as an open-source random instruction generator for RISC-V processor verification, and riscv_asm_program_gen generates complete RISC-V assembly programs and program sections used to verify RISC-V IP. RISC-V source class riscv_asm_program_gen, the brain behind ...

[5] C5: riscv_instr_gen_config randomization selects verification parameters such as ISA extension, privilege mode, instruction counts, and whether selected instruction classes are generated; gen_program coordinates program-section generation, directed streams, register initialization, assembly conversion, subprogram insertion, host-interface instructions, and trap-handling support. RISC-V source class riscv_asm_program_gen, the brain behind ...

[6] C6: gen_program and associated helpers produce complete RISC-V assembly programs with randomized instructions, randomized general-purpose-register selections, and different instruction patterns suitable for robust IP verification. RISC-V source class riscv_asm_program_gen, the brain behind ...

[7] C7: The cross-level approach was evaluated on the 32-bit pipelined RISC-V core of MINRES The Good Folk Series, found several serious bugs, and processed more than 200 million instructions per hour on a standard laptop. [PDF] Efficient Cross-Level Testing for Processor Verification: A RISC-V ...