riscv_instr_base_test

CodeArtifact

riscv_instr_base_test is a riscv-dv test artifact identified as riscv_instr_base_test.sv. It randomizes riscv_instr_gen_config, which determines key random-instruction-generation settings such as enabled RISC-V extensions, supported privilege mode, main/subprogram instruction counts, and suppression flags for instructions such as ebreak, dret, fence, and wfi.

First seen 5/26/2026

Last seen 5/28/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

riscv_instr_base_test refers to the riscv_instr_base_test.sv test in the open-source CHIPS Alliance riscv-dv RISC-V random instruction generator environment. In the documented generation flow, this test is the point from which the riscv_instr_gen_config class is randomized. That randomized configuration drives major stimulus-generation choices used later when generating RISC-V assembly programs for processor verification. [C1]

Role in the riscv-dv flow

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NEIGHBORHOOD

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RELATIONSHIPS

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riscv_instr_gen_config uses → 100% 2e

riscv_instr_base_test randomizes riscv_instr_gen_config to configure the test.

riscv-dv part of → 95% 1e

riscv_instr_base_test is a base test class within riscv-dv.

LINKED ENTITIES

1 links

riscv_instr_gen_config randomizes The evidence states that the class riscv_instr_gen_config is randomized from the test riscv_instr_base_test.sv.

CITATIONS

4 sources

4 citations — click to collapse

[1] riscv_instr_base_test.sv randomizes riscv_instr_gen_config, which determines RISC-V extension selection, supported privilege mode, main/subprogram instruction counts, and suppression flags such as no_ebreak, no_dret, no_fence, and no_wfi. RISC-V source class riscv_asm_program_gen, the brain behind ...

[2] The open-source CHIPS Alliance riscv-dv environment provides a SystemVerilog UVM-based class structure for RISC-V IP verification and generates assembly-program sections including initialization, instruction, data, stack, page table, interrupt, and exception-handling sections. RISC-V source class riscv_asm_program_gen, the brain behind ...

[3] Additional configuration variables can be set true or false based on DUT features and testbench stimulus-generation requirements. RISC-V source class riscv_asm_program_gen, the brain behind ...

[4] riscv_asm_program_gen.sv contains gen_program(), which generates program sections and calls functions including get_directed_instr_stream(), gen_program_header(), init_gpr(), and directed-instruction-stream generation. RISC-V source class riscv_asm_program_gen, the brain behind ...