Overview

riscv_instr_base_test refers to the riscv_instr_base_test.sv test in the open-source CHIPS Alliance riscv-dv RISC-V random instruction generator environment. In the documented generation flow, this test is the point from which the riscv_instr_gen_config class is randomized. That randomized configuration drives major stimulus-generation choices used later when generating RISC-V assembly programs for processor verification. [C1]

Role in the riscv-dv flow

The surrounding riscv-dv environment is described as an open-source, SystemVerilog UVM-based class structure for RISC-V IP verification. Its generated random tests can be run with a design IP, and the assembly program generated by the environment includes sections such as initialization, instruction, data, stack, page table, interrupt handling, and exception handling. [C2]

Within that flow, riscv_instr_base_test.sv randomizes riscv_instr_gen_config before assembly generation. This randomization selects or constrains several high-level test characteristics, including:

• the RISC-V extension set being exercised;
• the supported privilege mode;
• instruction counts in the main program and subprograms;
• whether break instructions are suppressed via no_ebreak;
• related suppression/configuration flags such as no_dret, no_fence, and no_wfi. [C1]

The same evidence notes that additional Boolean variables can be set according to DUT features and testbench stimulus-generation requirements, making riscv_instr_base_test.sv part of the configurable test setup rather than the assembly-emission logic itself. [C3]

Relationship to program generation

After configuration randomization, the documented assembly-generation flow centers on riscv_asm_program_gen.sv, whose gen_program() function generates the program sections and calls subordinate functions such as get_directed_instr_stream(), gen_program_header(), init_gpr(), and directed-instruction-stream generation. [C4]

Because riscv_instr_base_test.sv randomizes riscv_instr_gen_config, its primary technical significance is that it establishes generation parameters consumed by the broader riscv-dv program-generation flow. The evidence specifically ties those parameters to extension selection, privilege support, instruction-count choices, and instruction-suppression controls. [C1]

Key configuration outputs