Control and Status Registers (CSRs)

Concept

Control and Status Registers (CSRs) are special-purpose processor registers that hold control and status state, including additional instruction results. In RISC-V, CSRs enable trap handling and environment interaction as part of the privileged architecture. CSRs are relevant to verification both as a target of test generation and as a coverage/observation signal for exploring processor state.

First seen 5/29/2026

Last seen 6/7/2026

Evidence 4 chunks

Wiki v2

WIKI

Definition

Control and Status Registers (CSRs) are processor registers used to hold control and status information, as well as additional instruction results. In the RISC-V architecture, CSRs are special-purpose registers that, for example, enable trap handling and environment interaction, and they are specified as part of the RISC-V privileged architecture specification.

Role in RISC-V verification

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RELATIONSHIPS

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RISC-V Instruction Set Architecture part of → 95% 3e

CSRs are part of the RISC-V ISA, storing additional instruction results.

RISC-V part of → 100% 3e

CSRs are part of the RISC-V instruction set, enabling hardware/software interactions.

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 95% 2e

The paper supports CSR instructions in its instruction stream generation.

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← mentions 90% 1e

The paper mentions CSRs as instructions supported in its unrestricted instruction stream.

Endless Instruction Stream ← uses 90% 1e

Endless instruction streams include arbitrary CSR instructions without restrictions.

riscv-dv ← uses 85% 1e

RISC-V DV tracks changes to CSRs in its execution trace.

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CITATIONS

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[1] RISC-V provides Control and Status Registers (CSRs), which are special purpose registers that for example enable trap handling and environment interaction, and are described as part of the RISC-V privileged architecture specification. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion

[2] RISC-V DV supports additional specialized test strategies that focus on testing of CSRs, interrupts, and the MMU, beyond the five default test strategies used in the RV32IC evaluation. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion

[3] The RISC-V DV trace format records changes of the internal simulation state, including the program counter, changes to a GPR or CSR, and a disassembly of the executed instruction, and the framework can compute functional coverage information using SystemVerilog covergroup definitions. Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion

[4] In ProcessorFuzz, CSRs are in charge of controlling and holding the state of the processor, so transitions in CSRs indicate a new processor state; guiding the fuzzer based on this feedback enables exploration of new processor states. ProcessorFuzz: Guiding Processor Fuzzing using Control and Status Registers