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Bus Interface

Concept ☆ WATCH ⎘ SHARE

First seen 7/20/2026

Last seen 7/20/2026

Evidence 1 chunks

01

NEIGHBORHOOD

7 nodes · 11 edges

graph · Bus Interface · depth=1

02

RELATIONSHIPS

6 connections

Control and Status Registers ← uses 90% 1e evidence

CSRs usually interface to a processor bus, requiring a bus interface design.

IDesignSpec Suite ← introduces 90% 1e evidence

IDesignSpec Suite generates bus interfaces such as APB, AHB, AXI4, and TileLink.

APB ← part of 90% 1e evidence

APB is one of the bus interfaces supported in CSR design.

AHB ← part of 90% 1e evidence

AHB is one of the bus interfaces supported in CSR design.

AXI4 ← part of 90% 1e evidence

AXI4 is one of the bus interfaces supported in CSR design.

TileLink ← part of 90% 1e evidence

TileLink is one of the bus interfaces supported in CSR design.