RISC-V BOOM

Tool

First seen 7/5/2026

Last seen 7/5/2026

Evidence 8 chunks

NEIGHBORHOOD

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8 connections

RISC-V implements → 100% 2e

RISC-V BOOM is an open-source RISC-V processor that implements the RISC-V ISA.

Bitmap Update Queue ← part of 100% 2e

The BUQ is added to the RISC-V BOOM core as part of SNAP's hardware modifications.

Trace Decision Logic ← part of 100% 2e

Trace decision logic is added to the BOOM front-end Fetch Stage.

SNAP ← uses 100% 2e

SNAP is prototyped on top of the RISC-V BOOM core.

SNAP adds new CSRs to the RISC-V BOOM core for hardware-software interface.

out-of-order execution implements → 100% 1e

RISC-V BOOM is an out-of-order processor core with modern performance optimizations.

Branch Prediction implements → 100% 1e

RISC-V BOOM implements a gshare branch predictor as part of its front-end.

speculative execution implements → 85% 1e

Modern CPU architectures including BOOM adopt speculative execution for performance.