clock domain crossing

Clock Domain Crossing (CDC)

Concept

Clock Domain Crossing (CDC) refers to the transfer of data or signals between separate clock domains within a digital design. CDC paths are susceptible to metastability, requiring synchronization primitives and dedicated verification flows to ensure functional correctness.

First seen 7/16/2026

Last seen 7/20/2026

Evidence 2 chunks

Wiki v1

WIKI

Clock Domain Crossing (CDC)

Definition

A Clock Domain Crossing (CDC) occurs when a signal, data word, or control signal generated in one clock domain is consumed in another clock domain that operates asynchronously (i.e., with an unrelated or derived clock frequency/phase). SoC and FPGA designs frequently contain multiple asynchronous clock domains, particularly under the Globally-Asynchronous Locally-Synchronous (GALS) power-management approach used to improve energy efficiency.

Metastability and Functional Risk

When a signal transitions near the sampling edge of a receiving flip-flop in another domain, the receiving storage element can enter a metastable state, potentially propagating an indeterminate logic value downstream. CDC paths are therefore prone to metastability-induced functional bugs. Per the formal-verification literature on CDC, conventional methods such as register-transfer-level (RTL) simulation and static timing analysis are not sufficient on their own to catch every CDC issue, leaving verification gaps. CDC-related bugs are among the most common causes of costly silicon re-spins.

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NEIGHBORHOOD

2 nodes · 1 edges

graph · clock domain crossing · depth=1

RELATIONSHIPS

2 connections

prim_flop_2sync uses → 90% 1e

Clock domain crossing synchronization flops must use prim_flop_2sync behavioral macros.

Control and Status Registers ← uses 90% 1e

CSR bus interfaces may require CDC logic between the bus clock domain and the interface clock domain.

LINKED ENTITIES

1 links

prim_flop_2sync USES Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] SoC designs often operate on multiple asynchronous clock domains, creating CDC paths prone to metastability effects. Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)

[2] Conventional verification methods such as RTL simulation and static timing analysis are not sufficient to fully address CDC issues, and CDC-related bugs are common causes of silicon re-spins. Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)

[3] OpenTitan sign-off requires CDC synchronization flops to use behavioral synchronization macros (e.g. prim_flop_2sync) instead of manually created flops. Signoff Checklist - OpenTitan Documentation

[4] A CDC checking run must be set up when tooling is available, show no must-fix errors, and have any remaining issues captured in a reviewed waiver file. Signoff Checklist - OpenTitan Documentation

[5] A distributed settings-register memory architecture can be used to support clock-domain crossing and dynamic partial reconfiguration, reducing resource cost. A distributed memory, local configuration technique for re-configurable logic designs