Hybrid Automata and Formal Modeling for Safety-Critical RISC-V Control Systems

Paper

First seen 7/16/2026

Last seen 7/16/2026

Evidence 3 chunks

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The paper maps control logic to hybrid automata for cyber-physical applications, achieving formal guarantees for safety properties.

Uppaal uses → 88% 1e

The paper uses model checking tools like Uppaal to check temporal logic properties of RISC-V pipelines.

HyTech uses → 88% 1e

The paper uses model checking tools like HyTech to check temporal logic properties of RISC-V pipelines.

Temporal Logic uses → 93% 1e

Safety criteria like liveness, deadlock-freedom, and finite latency are written as temporal logic features and checked by model checking tools.

Pipelined CPU evaluates → 93% 1e

The paper uses a Hybrid Automata model to check RISC-V pipelines, with states Fetch, Decode, Execute, Memory, and WriteBack.

The review paper summarizes the Hybrid Automata paper on safety-critical RISC-V control systems.