RV32I

ISA

RV32I is the 32-bit base integer instruction-set variant of RISC-V without optional extensions. It defines 32 general-purpose 32-bit registers, with x0 hardwired to zero, and includes computational, load/store, and branch/jump instruction classes that operate on source and destination registers and immediate fields.

First seen 5/25/2026

Last seen 5/25/2026

Evidence 3 chunks

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WIKI

Overview

RV32I is the 32-bit form of the mandatory RISC-V base integer instruction set. In the RISC-V naming scheme, the base integer instruction set is denoted RV32I, RV64I, or RV128I according to register width, while optional extensions are denoted by single letters such as M for integer multiplication and division and C for compressed instructions. RV32I denotes a 32-bit core without extensions. [C1]

Register model

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RISC-V base_integer_variant_of Evidence states that RISC-V consists of mandatory base integer instruction sets denoted RV32I, RV64I, or RV128I, and that RV32I denotes a 32-bit core without extensions.

CITATIONS

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10 citations — click to expand

[1] RV32I is the 32-bit RISC-V base integer instruction set without optional extensions; RISC-V base integer sets are denoted RV32I, RV64I, or RV128I, and optional extensions use letters such as M and C.

[2] RV32I has 32 general-purpose registers x0 through x31, x0 is hardwired to zero, and each register is 32 bits wide.

[3] Writing to x0 does not change register state; the evidence gives add x0, x2, x3 as an example where no register value changes because x0 is always zero. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[4] RV32I instructions are grouped into computational, load/store, and branch/jump classes and access RS1, RS2, RD, and immediates.

[5] The instruction add x1, x2, x3 reads x2 and x3, adds them, and writes the result to x1. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[6] RV32I has I-, S-, B-, U-, and J-type immediates; I-type is a signed 12-bit immediate with range [-2048 ... 2047].

[7] LWU is described as a pure RV64I instruction and invalid in RV32I; c.slli is treated as illegal when compressed instructions are disabled. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[8] The unprivileged ISA specification defines format and semantics for the base ISA and extensions; the privileged architecture specification covers environment interaction, operating-system execution, and trap handling.

[9] Cross-level RV32I verification can compare ISS and RTL-core register values after completed instruction execution; this is difficult for pipelined RTL cores, and comparing only when register values changed can reduce false mismatches and unnecessary comparisons. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[10] In a coverage-guided fuzzing setup, an execution controller detects probable infinite loops when a repeated program-counter address occurs with unchanged register values and sets a hard ISS execution limit of 10,000 instructions. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing