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RV32I

ISA WIKI v2 · 5/27/2026

RV32I is the 32-bit base integer instruction-set variant of RISC-V without optional extensions. It defines 32 general-purpose 32-bit registers, with x0 hardwired to zero, and includes computational, load/store, and branch/jump instruction classes that operate on source and destination registers and immediate fields.

Overview

RV32I is the 32-bit form of the mandatory RISC-V base integer instruction set. In the RISC-V naming scheme, the base integer instruction set is denoted RV32I, RV64I, or RV128I according to register width, while optional extensions are denoted by single letters such as M for integer multiplication and division and C for compressed instructions. RV32I denotes a 32-bit core without extensions. [C1]

Register model

RV32I has 32 general-purpose registers named x0 through x31. Register x0 is hardwired to zero, and each register is 32 bits wide. [C2]

The hardwired-zero behavior of x0 is also relevant in verification: an instruction such as add x0, x2, x3 does not change architectural register state because the destination is x0. [C3]

Instruction operands and classes

RV32I instructions are grouped into classes such as computational, load/store, and branch/jump instructions. They operate using source registers RS1 and RS2, a destination register RD, and immediate fields. [C4]

For example, an add x1, x2, x3 instruction reads x2 and x3, adds their values, and writes the result to x1. [C5]

Immediate encodings

RV32I has five immediate types: I-type, S-type, B-type, U-type, and J-type. Immediate fields can differ in size and signedness. For example, an I-type immediate is a signed 12-bit value with range [-2048 ... 2047]. [C6]

Boundary with other RISC-V variants and extensions

Instructions outside the RV32I base set are illegal for an RV32I-only implementation. One verification example describes LWU as a pure RV64I instruction and therefore invalid in RV32I. The same example treats a compressed instruction, c.slli, as illegal when compressed instructions are disabled. [C7]

Specification context

The format and semantics of the RISC-V base ISA and extensions are defined in the unprivileged ISA specification. The privileged architecture specification covers additional functionality needed for environment interaction, operating-system execution, and trap handling. [C8]

Verification context

RV32I is commonly used as a target for processor verification examples. In cross-level verification, an instruction-set simulator (ISS) and an RTL core can be compared by observing architectural register values after instructions have completed. This is especially challenging for pipelined RTL cores, because a pipelined core may not expose a general signal indicating complete instruction execution. One described approach compares register values only at synchronization points where register values actually changed, reducing false mismatches and avoiding unnecessary comparisons. [C9]

Coverage-guided fuzzing work has also used RV32I instruction streams for verification. In one setup, test vectors are interpreted as endless instruction streams, so the execution controller detects probable infinite loops when a new program-counter address equals an already executed address and register values are unchanged; it also applies a hard limit of 10,000 ISS instruction executions. [C10]

LINKED ENTITIES

1 links
RISC-V base_integer_variant_of

CITATIONS

10 sources
10 citations
[1] RV32I is the 32-bit RISC-V base integer instruction set without optional extensions; RISC-V base integer sets are denoted RV32I, RV64I, or RV128I, and optional extensions use letters such as M and C.
[2] RV32I has 32 general-purpose registers x0 through x31, x0 is hardwired to zero, and each register is 32 bits wide.
[3] Writing to x0 does not change register state; the evidence gives add x0, x2, x3 as an example where no register value changes because x0 is always zero. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[4] RV32I instructions are grouped into computational, load/store, and branch/jump classes and access RS1, RS2, RD, and immediates.
[5] The instruction add x1, x2, x3 reads x2 and x3, adds them, and writes the result to x1. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[6] RV32I has I-, S-, B-, U-, and J-type immediates; I-type is a signed 12-bit immediate with range [-2048 ... 2047].
[7] LWU is described as a pure RV64I instruction and invalid in RV32I; c.slli is treated as illegal when compressed instructions are disabled. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[8] The unprivileged ISA specification defines format and semantics for the base ISA and extensions; the privileged architecture specification covers environment interaction, operating-system execution, and trap handling.
[9] Cross-level RV32I verification can compare ISS and RTL-core register values after completed instruction execution; this is difficult for pipelined RTL cores, and comparing only when register values changed can reduce false mismatches and unnecessary comparisons. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[10] In a coverage-guided fuzzing setup, an execution controller detects probable infinite loops when a repeated program-counter address occurs with unchanged register values and sets a hard ISS execution limit of 10,000 instructions. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

VERSION HISTORY

v2 · 5/27/2026 · gpt-5.5 (current)
v1 · 5/25/2026 · gpt-5.5