Masking

Technique

Masking is a secret-sharing-based countermeasure against physical side-channel attacks (e.g., power analysis, electromagnetic emanation analysis) on cryptographic implementations. It decomposes secret values into multiple randomized shares so that any observation bounded by a threshold number of intermediate values is statistically independent of the secret. Originating with the Ishai–Sahai–Wagner (ISW) construction, masking has been extended to many software and hardware variants, but its security guarantees in practice can be degraded by hardware effects such as glitches, register transitions, and microarchitectural components.

First seen 6/26/2026

Last seen 6/26/2026

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Masking

Overview

Masking is a widely deployed cryptographic implementation technique designed to thwart physical side-channel attacks, including power analysis and electromagnetic emanation (EM) analysis. By splitting sensitive intermediate values into multiple randomized shares, masking aims to ensure that an attacker observing up to a fixed number of intermediate values learns no statistical information about the underlying secret. It is a form of secret sharing applied at the algorithm level.

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Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches ← uses 82% 1e

Context establishes masking as the countermeasure whose security is being verified end-to-end.

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CITATIONS

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[1] Masking is a widely used countermeasure against physical side-channel attacks such as power or electromagnetic emanation analysis on cryptographic implementations. Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches

[2] Masking splits an algorithm's inputs and outputs into multiple intermediate values called shares; when splitting a secret into d ≥ t + 1 random shares, any set of at most t intermediate values must be statistically independent of any secret value. Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches

[3] Ishai, Sahai, and Wagner introduced a method to transform arbitrary algorithms into functionally equivalent masked algorithms, requiring each successive computation to emit leakage independent of previous computations. Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches

[4] Due to physical effects in integrated circuits, hardware power consumption correlates with computations from consecutive clock cycles, potentially breaking masked security guarantees; extended leakage models incorporating physical effects have been proposed to prevent reduction of security order. Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches

[5] Software-based masking implementations additionally suffer from leakages caused by microarchitectural components such as registers and pipeline structures. Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches

[6] Leakage contracts provide a formal separation between hardware and software verification of masked implementations, and recent work extends them to account for glitches and transitions, supporting end-to-end machine-checked verification from gate-level hardware up to masked software. Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches

[7] In formal fault-tolerance analysis, masking fault-tolerance means a system completely masks faults so they have no observable consequences for users; it can be captured via simulation relations on labeled transition systems and quantified as a directed pseudo-metric. Measuring Masking Fault-Tolerance

[8] In speech privacy research, content masking refers to concealing selected words/phrases in speech (e.g., via noise substitution, word deletion, or phone-sequence reversal) using a VQ-VAE and neural vocoder pipeline, distinct from cryptographic masking. Exploratory Evaluation of Speech Content Masking