Skip to content
STIMSMITH

Masking

Technique WIKI v1 · 6/26/2026

Masking is a secret-sharing-based countermeasure against physical side-channel attacks (e.g., power analysis, electromagnetic emanation analysis) on cryptographic implementations. It decomposes secret values into multiple randomized shares so that any observation bounded by a threshold number of intermediate values is statistically independent of the secret. Originating with the Ishai–Sahai–Wagner (ISW) construction, masking has been extended to many software and hardware variants, but its security guarantees in practice can be degraded by hardware effects such as glitches, register transitions, and microarchitectural components.

Masking

Overview

Masking is a widely deployed cryptographic implementation technique designed to thwart physical side-channel attacks, including power analysis and electromagnetic emanation (EM) analysis. By splitting sensitive intermediate values into multiple randomized shares, masking aims to ensure that an attacker observing up to a fixed number of intermediate values learns no statistical information about the underlying secret. It is a form of secret sharing applied at the algorithm level.

Security Definition

Masking splits an algorithm's inputs and outputs into multiple intermediate values called shares. Concretely, a secret is decomposed into d ≥ t + 1 random shares. The central security requirement is:

  • Any set of at most t intermediate values of the masked computation must be statistically independent of any secret value.
  • Consequently, an attacker with access to at most t intermediate values cannot learn any information about the secret.

The integer t is referred to as the security order of the masked implementation. Higher-order masking yields stronger resistance but incurs increased overhead in shares, randomness, and computation.

The ISW Construction

The seminal method for building masked software implementations was introduced by Ishai, Sahai, and Wagner [ISW03]. Their scheme transforms an arbitrary (Boolean-circuit-style) algorithm into a functionally equivalent masked algorithm. Its core requirement is that each successive computation must emit leakage that is independent of previous computations, so that the independence of shares is preserved across operations.

Challenges in Hardware Realizations

In real hardware, the ISW independence requirement is generally violated:

  • Physical effects in integrated circuits cause the power consumption of a design to correlate with computations from consecutive clock cycles, which can break the statistical independence assumed by the masking proof.
  • Glitches — transient, unintended switching activity in CMOS circuits — produce ephemeral leakages that combine multiple shares within a single clock cycle, potentially reducing the effective security order.
  • Transitions between successive register states contribute additional leakage that must be modeled.
  • Microarchitectural components of CPUs (registers, pipeline stages, ALUs) introduce additional software-visible leakage sources in software-based masking.

To address these issues, extended leakage models have been proposed that explicitly incorporate physical effects such as glitches and transitions in order to prevent the order of security from being silently reduced. Formal frameworks such as leakage contracts have been introduced to provide a clean separation between hardware and software verification of masked implementations, enabling end-to-end machine-checked security proofs from the gate level up to masked C code.

Broader Uses of the Term "Masking"

While the dominant technical meaning in the cryptographic hardware community is the side-channel countermeasure described above, the term masking is used in adjacent technical areas with different, unrelated meanings:

  • Masking fault-tolerance — In the formal analysis of fault-tolerant systems (e.g., critical control systems), a system is said to exhibit masking fault-tolerance if it can completely absorb faults so that they have no observable consequences to its users. This notion can be captured via simulation relations between labeled transition systems and measured quantitatively as a directed pseudo-metric.
  • Content masking in speech — In speech privacy research, content masking refers to concealing selected words or phrases in spoken audio (e.g., via noise substitution, word deletion, or phone-sequence reversal) to protect information carried by speech content rather than speaker identity.

These usages share only the intuition of "hiding" or "neutralizing" some signal; they are not based on secret sharing and should not be conflated with cryptographic masking.

Role in Hardware/Software Co-Verification

Because masked software's security argument depends on assumptions about hardware leakage, leakage contracts have been proposed as a single source of truth that both hardware designers and software cryptographers can target. Recent work extends such contracts to account for glitches and transitions and applies them to off-the-shelf cores such as the RISC-V Ibex, demonstrating end-to-end verified masked implementations without modifying the underlying hardware design.

LINKED ENTITIES

1 links
Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches USES

CITATIONS

8 sources
8 citations
[1] Masking is a widely used countermeasure against physical side-channel attacks such as power or electromagnetic emanation analysis on cryptographic implementations. Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches
[2] Masking splits an algorithm's inputs and outputs into multiple intermediate values called shares; when splitting a secret into d ≥ t + 1 random shares, any set of at most t intermediate values must be statistically independent of any secret value. Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches
[3] Ishai, Sahai, and Wagner introduced a method to transform arbitrary algorithms into functionally equivalent masked algorithms, requiring each successive computation to emit leakage independent of previous computations. Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches
[4] Due to physical effects in integrated circuits, hardware power consumption correlates with computations from consecutive clock cycles, potentially breaking masked security guarantees; extended leakage models incorporating physical effects have been proposed to prevent reduction of security order. Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches
[5] Software-based masking implementations additionally suffer from leakages caused by microarchitectural components such as registers and pipeline structures. Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches
[6] Leakage contracts provide a formal separation between hardware and software verification of masked implementations, and recent work extends them to account for glitches and transitions, supporting end-to-end machine-checked verification from gate-level hardware up to masked software. Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches
[7] In formal fault-tolerance analysis, masking fault-tolerance means a system completely masks faults so they have no observable consequences for users; it can be captured via simulation relations on labeled transition systems and quantified as a directed pseudo-metric. Measuring Masking Fault-Tolerance
[8] In speech privacy research, content masking refers to concealing selected words/phrases in speech (e.g., via noise substitution, word deletion, or phone-sequence reversal) using a VQ-VAE and neural vocoder pipeline, distinct from cryptographic masking. Exploratory Evaluation of Speech Content Masking