UC Berkeley — STIMSMITH

UC Berkeley

Organization

UC Berkeley is cited in the provided evidence as the organization that open sourced Rocket, described as the world’s first open-source RISC-V processor, and as the home of the Berkeley Architecture Research group that develops and maintains BOOM. The evidence also mentions a UC Berkeley-developed GitHub repository of RISC-V unit tests.

First seen 5/27/2026

Last seen 6/6/2026

Evidence 5 chunks

Wiki v2

WIKI

Overview

UC Berkeley appears in the provided evidence through RISC-V processor and verification artifacts. In the MorFuzz evaluation, Rocket is described as the world’s first RISC-V processor open sourced by UC Berkeley. In a separate MICRO-54 processor-verification paper, BOOM is described as developed and maintained at UC Berkeley’s Berkeley Architecture Research group.

RISC-V processor artifacts

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NEIGHBORHOOD

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RELATIONSHIPS

9 connections

RISC-V ISA ← mentions 90% 1e

RISC-V was developed at UC Berkeley.

Rocket ← authored by 100% 1e

Rocket is the world's first RISC-V processor open sourced by UC Berkeley.

BOOM ← authored by 90% 1e

BOOM is the Berkeley Out-of-Order Machine developed at UC Berkeley.

RISC-V Instruction Set Architecture ← part of 90% 1e

RISC-V was developed at UC Berkeley.

RISC-V Instruction Set Architecture introduces → 95% 1e

RISC-V was developed at UC Berkeley.

RISC-V ISA ← part of 95% 1e

RISC-V was developed at UC Berkeley.

RISC-V ← derived from 100% 1e

RISC-V was developed at UC Berkeley.

Rocket ← published by 100% 1e

Rocket was open sourced by UC Berkeley.

BOOM ← published by 90% 1e

BOOM is a Berkeley Out-of-Order Machine, developed at UC Berkeley.

CITATIONS

7 sources

7 citations — click to expand

[1] Rocket is described as the world's first RISC-V processor open sourced by UC Berkeley. MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

[2] Rocket is a five-stage, single-issue, in-order scalar processor written in Chisel, supports delayed write-back, actively supports extensions including hypervisor and cryptography, has been taped out dozens of times, and has been extensively verified by academic and industrial groups. MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

[3] BOOM is described by MorFuzz as the third generation of the Berkeley Out-of-Order Machine, an out-of-order superscalar processor written in Chisel; MorFuzz used the triple-issue LargeBoom configuration and noted that the latest BOOM had been verified on FPGA. MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

[4] BOOM is developed and maintained at UC Berkeley's Berkeley Architecture Research group, is written in Chisel, can generate Verilog BOOM designs of varying complexity, implements the 64-bit RISC-V instruction set, and was evaluated as a default MediumBoomConfig 2-wide out-of-order core in the MICRO-54 paper. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[5] One more complex BOOM configuration had been taped out in 28nm technology. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[6] A GitHub repository developed in UC Berkeley provides unit tests that sweep through the base instructions defined in the RISC-V ISA, and the MICRO-54 paper characterizes such tests as checking only basic functionality. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...

[7] MorFuzz evaluated Rocket and BOOM among three RISC-V processors to demonstrate compatibility across different RISC-V microarchitectures, and all processors in the evaluation were capable of booting and running Linux. MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation