RISC-V Instruction Set Architecture — STIMSMITH

RISC-V Instruction Set Architecture

Concept

The RISC-V instruction set architecture, as described in the MorFuzz evidence, uses 16-bit compressed instructions and 32-bit non-compressed instructions. Its instruction formats are composed of opcode-related and operand-related fields, including opcode, op, funct, rs, imm, and rd fields. The MorFuzz processor-fuzzing work implemented a prototype on the RISC-V architecture and used RISC-V instruction formats in its verification context.

First seen 5/27/2026

Last seen 6/3/2026

Evidence 12 chunks

Wiki v1

WIKI

Overview

RISC-V instructions currently have two valid lengths: 16-bit compressed instructions and 32-bit instructions for all other instructions. The cited MorFuzz paper presents 15 RISC-V instruction formats, each made up of multiple fields. [Instruction lengths and formats]

Instruction length and format decoding

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NEIGHBORHOOD

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RELATIONSHIPS

7 connections

Control and Status Registers (CSRs) ← part of 95% 3e

CSRs are part of the RISC-V ISA, storing additional instruction results.

RV32I Base Integer ISA ← part of 100% 2e

RV32I is the 32-bit base integer ISA that is part of the RISC-V ISA family.

MorFuzz ← uses 100% 2e

MorFuzz targets the RISC-V ISA and is implemented on the RISC-V architecture.

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← evaluates 95% 2e

The paper evaluates verification for a RISC-V processor.

MINRES The Good Core (TGC) ← implements 100% 2e

The MINRES TGC is a 32-bit RISC-V processor implementing the RISC-V ISA.

UC Berkeley part of → 90% 1e

RISC-V was developed at UC Berkeley.

UC Berkeley ← introduces 95% 1e

RISC-V was developed at UC Berkeley.

LINKED ENTITIES

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MorFuzz USES Extracted graph relationship

CITATIONS

7 sources

7 citations — click to expand

[1] Instruction lengths and formats MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

[2] Encoding determinants MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

[3] Field categories MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

[4] Instruction formats list MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

[5] Processor verification workflow MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

[6] MorFuzz RISC-V implementation MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

[7] MorFuzz evaluation results MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation