Overview

UC Berkeley appears in the provided evidence through RISC-V processor and verification artifacts. In the MorFuzz evaluation, Rocket is described as the world’s first RISC-V processor open sourced by UC Berkeley. In a separate MICRO-54 processor-verification paper, BOOM is described as developed and maintained at UC Berkeley’s Berkeley Architecture Research group.

RISC-V processor artifacts

Rocket

Rocket is described in the MorFuzz paper as a five-stage, single-issue, in-order scalar processor written in Chisel. The same source states that Rocket supports delayed write-back, which allows long-latency instructions to commit without carrying write-back data. Rocket is also described as actively supporting extensions such as hypervisor and cryptography support, having been taped out dozens of times, and having been extensively verified by academic and industrial groups.

BOOM

BOOM, the Berkeley Out-of-Order Machine, is described in the MorFuzz paper as a Chisel-based out-of-order superscalar processor and the third generation of BOOM. MorFuzz used a triple-issue LargeBoom configuration in its experiments and noted that the latest BOOM had been verified on FPGA.

A separate MICRO-54 paper describes BOOM as developed and maintained at UC Berkeley’s Berkeley Architecture Research group. In that paper, BOOM is presented as a Chisel hardware-construction-language generator that can produce Verilog BOOM designs with varying complexity. The paper states that generated BOOM cores implement the 64-bit RISC-V instruction set, that its evaluation used the default MediumBoomConfig as a 2-wide out-of-order core, and that one more complex BOOM configuration had been taped out in 28nm technology.

Verification resources and evaluation context

The MICRO-54 paper also mentions a GitHub repository developed in UC Berkeley that provides unit tests sweeping through the base instructions defined in the RISC-V ISA; the paper characterizes these resources as checking only basic functionality.

In MorFuzz, Rocket and BOOM were two of three RISC-V processors used to demonstrate compatibility across different RISC-V microarchitectures. The paper states that all processors in that evaluation were capable of booting and running Linux.