RISCSmith
ToolFirst seen 7/1/2026
Last seen 7/1/2026
Evidence 16 chunks
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31 connectionsRISCSmith is directly compared with RISCV-DV in experiments, outperforming it in bugs found and coverage.
RISCSmith instruments RISC-V implementation source with lightweight logging hooks into the RTL.
RISCSmith records per-instruction register updates, memory writes, and exceptions with minimal overhead during simulation.
RISCSmith automatically builds rich instruction models by parsing the RISC-V UnifiedDB.
RISCSmith implements rich instruction construction as a core technique for generating high-quality test programs.
RISCSmith automatically constructs programs that initialize register and memory contexts.
RISCSmith uses the RISC-V UnifiedDB as its primary data source for automated instruction model construction.
RISCSmith implements on-the-fly differential analysis to detect behavioral divergences between CPU implementations.
RISCSmith is directly compared with Cascade in experiments, outperforming it in bugs found and coverage.
RISCSmith constructs strongly typed instruction models that capture operand roles, type constraints, and runtime semantics.
RISCSmith was evaluated on Rocket and discovered bugs in it.
RISCSmith conducts differential testing through a three-stage pipeline comparing target implementations against reference models.
RISCSmith was evaluated on XiangShan and discovered bugs in it.
RISCSmith uses Verilator to compile and simulate instrumented RISC-V implementations.
RISCSmith uses Spike as the golden reference model for differential comparison.
RISCSmith was evaluated on Kronos and discovered bugs in it.
RISCSmith targets RISC-V CPUs and uses RISC-V instruction specifications for modeling.
RISCSmith instruments RTL implementations and simulates them to detect bugs.
RISCSmith is used in the context of pre-silicon verification to detect bugs before tape-out.
RISCSmith was evaluated on PicoRV32 and discovered bugs in it.
RISCSmith: Finding RISC-V CPU Bugs via Rich Instruction Construction and On-the-fly Differential Analysis ← introduces 100% 2e
The paper proposes and introduces RISCSmith as a new fuzzing framework for detecting RISC-V CPU bugs.
RISCSmith was evaluated on CVA6 and discovered multiple bugs in it.
RISCSmith was evaluated on VexRiscv and discovered bugs in it.
RISCSmith models inter-instruction data dependencies in generated programs.
RISCSmith targets CPU implementations as the subject of its fuzzing.
RISCSmith applies a binary search-based minimization algorithm to isolate the shortest instruction sequence that triggers a bug.
RISCSmith inserts exception carry-on templates as part of its test program generation.
RISCSmith uses the GNU RISC-V toolchain to assemble and compile generated test programs.
RISCSmith is a hardware fuzzing framework targeting RISC-V CPUs.
RISCSmith collects coverage data to measure and improve test effectiveness.
The paper positions RISCSmith as an alternative to formal verification, which is costly.