RISCSmith: Finding RISC-V CPU Bugs via Rich Instruction Construction and On-the-fly Differential Analysis
PaperFirst seen 7/1/2026
Last seen 7/1/2026
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14 connectionsThe paper proposes and introduces RISCSmith as a new fuzzing framework for detecting RISC-V CPU bugs.
Xudong Zhang is listed as a co-author of the paper.
Yuanliang Chen is listed as a corresponding author of the paper.
Zhen Yan is listed as a co-author of the paper.
Fuchen Ma is listed as a co-author of the paper.
Dalong Shi is listed as a co-author from Aviation Industry Corporation of China.
Yu Jiang is listed as a corresponding author of the paper.
The paper mentions DIFUZZRTL as related work in differential testing.
The paper mentions DLFuzz as related work in differential testing.
The paper mentions TheHuzz as related CPU fuzzing work.
The paper mentions MorFuzz as a related CPU fuzzer that relies on manually built instruction models.
The paper mentions INSTILLER as related work in RTL fuzzing.
Zehong Yu is listed as a co-author of the paper.
The paper mentions BOOM as a RISC-V CPU where existing fuzzers have uncovered bugs.