RTL Simulation
ConceptRTL simulation is used in simulation-based hardware verification and processor fuzzing to execute a hardware design-under-test by translating its RTL or Verilog representation into a host executable binary. In the MorFuzz work, RTL simulation is performed with Synopsys VCS, while coverage instrumentation is used during simulation to evaluate fuzzing inputs.
WIKI
Overview
RTL simulation is a hardware-simulation step used in dynamic, simulation-based verification of processor designs. In the cited processor-verification workflow, simulation-based verification uses tailored inputs to simulate the design under test (DUT) and check whether the DUT output meets expectations. The evidence contrasts this with static formal verification and notes that simulation-based verification is more prevalent in practice because formal verification has scaling limits on complex designs. [simulation-based-verification]