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STIMSMITH

Whisper

Tool

Whisper is a RISC-V instruction set simulator developed by Western Digital. Evidence from a processor-verification paper describes it as usable in co-simulation, with limitations relative to Open-Cosim: RV32-only support, no interrupt handling, and no checkpoint support. The RISCV-DV project also lists Whisper among the ISS targets it can use for co-simulation.

First seen 5/25/2026
Last seen 5/28/2026
Evidence 2 chunks
Wiki v2

WIKI

Whisper

Whisper is a RISC-V instruction set simulator developed by Western Digital. In the context of processor verification, it can be used in a co-simulation environment. A MICRO-54 paper comparing verification approaches describes Whisper as an ISS option, while noting that, relative to Open-Cosim, Whisper supports only RV32, does not handle interrupts, and has no support for checkpoints. [1]

Use in verification flows

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RELATIONSHIPS

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Western Digital ← uses 100% 1e
Whisper is the instruction set simulator developed by Western Digital.
Dromajo ← compares with 90% 1e
Dromajo is compared to Whisper as an alternative co-simulation reference model tool.
riscv-dv ← uses 1e
RISCV-DV uses whisper as a co-simulation ISS.
Co-simulation ← uses 1e
Co-simulation in RISCV-DV uses whisper as one of the supported ISS tools.
Co-simulation implements → 90% 1e
Whisper is an ISS developed by Western Digital that can be used for co-simulation.
Western Digital authored by → 100% 1e
Whisper was developed by Western Digital.
The paper compares Dromajo with Whisper, noting Whisper's limitations in interrupt and checkpoint support.

CITATIONS

3 sources
3 citations — click to collapse
[1] Whisper is a RISC-V instruction set simulator developed by Western Digital and usable in co-simulation environments. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...
[2] The cited comparison states that Whisper supports only RV32, does not handle interrupts, and has no checkpoint support relative to Open-Cosim. [PDF] Effective Processor Verification with Logic Fuzzer Enhanced Co ...
[3] RISCV-DV lists Whisper among multiple ISS backends supported for co-simulation. chipsalliance/riscv-dv