Whisper

Whisper is a RISC-V instruction set simulator developed by Western Digital. In the context of processor verification, it can be used in a co-simulation environment. A MICRO-54 paper comparing verification approaches describes Whisper as an ISS option, while noting that, relative to Open-Cosim, Whisper supports only RV32, does not handle interrupts, and has no support for checkpoints. ^[1]

Use in verification flows

Whisper appears as one of the instruction set simulators supported by RISCV-DV, an open-source SystemVerilog/UVM instruction generator for RISC-V processor verification. RISCV-DV lists co-simulation with multiple ISS backends, including Spike, riscv-ovpsim, Whisper, and sail-riscv. ^[2]

Capabilities and limitations described in the evidence

The available evidence supports the following technical characterization:

• Role: RISC-V instruction set simulator. ^[1]
• Developer: Western Digital. ^[1]
• Verification use: Can be used in co-simulation environments. ^[1]
• RISCV-DV integration: Listed by RISCV-DV as a supported ISS for co-simulation. ^[2]
• Limitations noted by Kabylkas et al.: RV32-only support, no interrupt handling, and no checkpoint support relative to Open-Cosim. ^[1]

Relationship to co-simulation

The strongest supported relationship for Whisper in the provided evidence is its use as an ISS inside RISC-V co-simulation workflows. The MICRO-54 paper explicitly states that Whisper can be used in a co-simulation environment, and RISCV-DV lists it among ISS targets for co-simulation.