DPI

Concept

DPI (Direct Programming Interface) is the SystemVerilog call boundary used in the cited RISC-V verification flow to let Verilog/RTL simulation invoke external software-side components such as the Dromajo reference model and Logic Fuzzer table objects. It enables step-and-compare co-simulation, asynchronous interrupt handling, and redirection of RTL table accesses to fuzzer-managed structures.

First seen 5/28/2026

Last seen 8/14/2026

Evidence 6 chunks

Wiki v2

WIKI

Overview

In the cited RISC-V verification evidence, DPI is the mechanism used for calls between Verilog/RTL simulation and external software-side verification components. The DPI functions are described as the integration boundary that links RTL logic to a reference model and to fuzzer-backed structures. ^[1] ^[2]

The cited Imperas step-and-compare presentation identifies DPI as the technique that connects the testbench control block to the reference model so that the RISC-V RTL and reference model can be advanced and compared in lock-step. ^[2]

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NEIGHBORHOOD

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RELATIONSHIPS

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Logic Fuzzer ← uses 95% 2e

Logic Fuzzer uses DPI calls to interface with RTL during simulation.

Dromajo ← uses 95% 1e

Dromajo uses DPI calls for integration with RTL simulators.

table mutator ← uses 90% 1e

Table mutators are accessed through DPI from the RTL.

Step-and-Compare ← uses 85% 1e

The step-and-compare setup uses DPI to interface between SystemVerilog testbench and the reference model

LINKED ENTITIES

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Step-and-Compare USES Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] In the cited step-and-compare slides, DPI is shown as the boundary that lets a SystemVerilog testbench step the reference model and the RISC-V RTL together and compare their results. An introduction to RISC-V processor verification techniques

[2] The step-and-compare flow consists of a test program, a processor reference model, the RTL DUT and tracer, an RTL simulator, and step-and-compare logic that extracts data from each side and reports differences immediately. An introduction to RISC-V processor verification techniques

[3] The reference model is configured to select RISC-V ISA extensions, supports custom instructions and CSRs, can run in lock-step with the RTL simulator, can be stepped at significant events (retire, trap), and exposes functions to query its state for comparison. An introduction to RISC-V processor verification techniques

[4] The step-and-compare-with-asynchronous-events flow adds debug and interrupt drivers on top of the same step-and-compare logic and connects them to the testbench alongside the reference model. An introduction to RISC-V processor verification techniques

[5] In the Logic Fuzzer flow, a fuzzer object in Dromajo is configured to allocate a table with the same size as the corresponding RTL structure; the implementation side accesses that fuzzer table through the DPI instead of the RTL memory model. Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation

[6] During simulation the tables reached through the DPI are fuzzed randomly or with specific patterns, and the instruction-cache tag and data arrays are replaced with these table mutators. Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation