Step-and-Compare

Technique

First seen 8/14/2026

Last seen 8/14/2026

Evidence 3 chunks

NEIGHBORHOOD

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7 connections

Step-and-compare is one of the core techniques used in RISC-V design verification

Step-and-compare relies on a processor reference model that runs in lock-step with the RTL

Co-simulation uses → 90% 1e

Step-and-compare is implemented via co-simulation between the reference model and the RTL

DPI uses → 85% 1e

The step-and-compare setup uses DPI to interface between SystemVerilog testbench and the reference model

SystemVerilog uses → 90% 1e

The step-and-compare approach encapsulates the reference model in a SystemVerilog testbench

Step-and-compare with asynchronous events extends the basic step-and-compare to handle async events

ImperasDV ← implements 90% 1e

ImperasDV implements step-and-compare methodology through RVVI-API