asynchronous interrupts

Asynchronous interrupts

Concept

In RISC-V processor design verification, asynchronous interrupts are external stimuli that can fire at unpredictable points during execution, complicating reference-model comparison and motivating specialized trace and virtual-peripheral interfaces such as RVVI-TRACE and RVVI-VVP, as well as reference-emulator mechanisms (e.g., Dromajo's raise_interrupt) for keeping RTL and ISS control flow aligned.

First seen 5/28/2026

Last seen 8/3/2026

Evidence 5 chunks

Wiki v2

WIKI

Overview

In the RISC-V processor verification context, asynchronous interrupts are external stimuli that may fire unpredictably during execution, rather than at a fixed instruction boundary chosen by an offline trace-comparison flow. Because of that asynchronous behavior, a single interrupt can cause independently generated RTL and reference-model execution logs to diverge, even when the design behavior is otherwise intended. [interrupts-as-external-stimuli]

Impact on reference-model comparison

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NEIGHBORHOOD

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RELATIONSHIPS

3 connections

Dromajo ← uses 95% 2e

Dromajo supports handling of asynchronous interrupts during co-simulation.

RVVI-Trace ← uses 95% 1e

RVVI-TRACE includes capabilities for cores with asynchronous interrupts.

RVVI-VVP ← uses 90% 1e

RVVI-VVP includes timers to generate asynchronous interrupts.

LINKED ENTITIES

2 links

RVVI-Trace USES Extracted graph relationship

RVVI-VVP USES Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] Asynchronous interrupts are external stimuli that may fire randomly during execution and can cause RTL and reference-model logs to diverge. Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation

[2] Reference-model comparison must take into account all ISA architectural features and options including full asynchronous operation. RISC-V Verification Interface (RVVI)

[3] RVVI-TRACE supports simple in-order cores through multi-hart, multi-issue, out-of-order cores with asynchronous interrupts and debug modes. RISC-V Verification Interface (RVVI)

[4] RVVI-VVP defines testbench components including timers to generate asynchronous interrupts. RISC-V Verification Interface (RVVI)

[5] Co-simulation is synchronous, but interrupts are not; the flow must log interrupt entry and force Dromajo's control flow to match via the raise_interrupt() DPI wrapper, which communicates the cause and sets the trap vector. Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation