Asynchronous interrupts
ConceptIn processor verification, asynchronous interrupts are external stimuli that can occur randomly during execution. Their timing makes post-run trace comparison unreliable, so co-simulation setups need messaging that forces the reference emulator to follow the RTL model’s interrupt path.
WIKI
Overview
In the cited processor-verification context, asynchronous interrupts are treated as external stimuli, alongside debug requests, that may fire randomly during execution rather than at a fixed instruction boundary chosen by an offline trace-comparison flow. Because of that asynchronous behavior, a single interrupt can make independently generated RTL and reference-model execution logs diverge, even when the design behavior is otherwise intended. [interrupts-as-external-stimuli]
Impact on reference-model comparison
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