Interrupt handling appears in the provided evidence as both generated RISC-V trap-handler code and as a verification concern for asynchronous external stimuli. In riscv-dv, interrupt and exception handling are generated as assembly-program sections, including an mtvec_handler section with interrupt_handler and exception_handler definitions. In co-simulation, interrupts require explicit messaging because asynchronous events can make standalone trace comparison diverge; Dromajo supports this through mechanisms such as raise_interrupt(), which communicates the interrupt cause and sets the trap vector.

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