Overview

In the provided RISC-V verification evidence, interrupt handling is a trap-related part of generated assembly programs and a special case for reference-model co-simulation. The riscv-dv riscv_asm_program_gen class generates multiple assembly-program sections, including initialization, instruction, data, stack, page-table, interrupt-handling, and exception-handling sections.

Interrupt handling in generated RISC-V assembly

The riscv-dv assembly-generation flow treats interrupt handling as part of the generated program structure. The gen_program() function is described as the main entry point that generates all sections of a program by calling other riscv_asm_program_gen functions. After main-program and optional subprogram generation, host-interface code such as write_tohost and _exit is added through gen_section().

For trap-related code, the flow calls push_gpr_to_kernel_stack(), which pushes general-purpose registers onto a stack for trap handling. The generated program then uses gen_section() to select the mtvec_handler instruction section; that section contains both exception_handler and interrupt_handler definitions.

Why interrupts are special in verification

Interrupts are asynchronous external stimuli. The evidence notes that trace comparison can fail when testing external stimuli such as interrupts or debug requests: because the stimulus can fire randomly during execution, a single interrupt can make the execution logs of independently running models differ.

Co-simulation addresses this by running models in parallel and supporting communication between them. In such a setup, the RTL model can signal events to the reference model, and the reference model can be forced to follow the same interrupt-driven execution path.

Dromajo co-simulation behavior

Dromajo is presented as a RISC-V reference model that can boot Linux and handle external stimuli such as interrupts and debug requests. In the described RTL-Dromajo interaction, a step() DPI wrapper communicates program counter, instruction, and store data to Dromajo whenever a valid instruction is committed; Dromajo then commits one instruction and compares communicated data.

Because co-simulation is synchronous but interrupts are not, the evidence describes a separate raise_interrupt() DPI wrapper. When a core takes an interrupt, raise_interrupt() communicates the cause and sets the trap vector in Dromajo, allowing the interrupt trap-handler routines to be co-simulated.

Broader contexts

Interrupt handling also appears in operating-system and processor-controller research contexts in the provided public sources. A formal ARINC 653 operating-system specification includes interrupt handling among its modeled OS services and behaviors. In virtualized RISC-V mixed-criticality systems, interrupt virtualization is described as challenging because virtual guests need transparency while real-time features such as interrupt vectoring, nesting, and tail-chaining are preserved; the vCLIC work proposes a virtualization extension to the RISC-V CLIC fast interrupt controller for this setting.