CSR (Control and Status Register)

Concept

In the RISC-V processor-verification evidence, CSR stands for Control and Status Register: architectural state defined by the RISC-V ISA together with the special instructions used to access them. CSRs serve both as a verification target (compared as architectural state in Dromajo co-simulation, verified under external stimulus through the Ibex handshaking mechanism, and proposed as the next extension of the mutation-based Compliance Testing framework) and as a coverage/fuzzing signal in ProcessorFuzz, which introduces a CSR-transition coverage metric that monitors CSR state transitions to guide the fuzzer. The supplied public-context entries that use "CSR" for Corporate Social Responsibility or "CSRS" for a code-search model are unrelated to this article.

First seen 5/26/2026

Last seen 7/18/2026

Evidence 16 chunks

Wiki v5

WIKI

CSR (Control and Status Register)

In the supplied RISC-V processor-verification evidence, CSR denotes the RISC-V Control and Status Register: architectural state defined by the RISC-V ISA together with the special instructions used to access it. [C1] The acronym is consistently used in this ISA sense across the mutation-based compliance testing, Ibex co-simulation, and ProcessorFuzz sources; the public context entries that use "CSR" for Corporate Social Responsibility and "CSRS" for a code-search model are unrelated and are not the subject of this article. [P1][P2]

RISC-V ISA definition of CSRs

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NEIGHBORHOOD

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RELATIONSHIPS

12 connections

Mutation-based Compliance Testing for RISC-V ← mentions 90% 2e

The paper discusses CSRs as a future extension direction and in context of virtual memory.

riscv-dv ← implements 97% 2e

RISCV-DV includes privileged CSR setup randomization and test suite

Dromajo ← uses 100% 1e

Dromajo checkpoints include CSR state and leverages RISC-V debug spec for CSR manipulation.

handshaking mechanism ← uses 1e

The handshaking mechanism supports verification of correct CSR updates during external stimulus scenarios.

ProcessorFuzz ← uses 96% 1e

Monitoring CSR transitions is central to the tool’s guidance, indicating use of CSRs.

STING ← evaluates 93% 1e

STING stresses CSRs as part of its verification capability.

ProcessorFuzz: Guiding Processor Fuzzing using Control and Status Registers ← mentions 99% 1e

CSRs are central to the proposed coverage metric and guidance mechanism.

regtool uses → 95% 1e

CSR checks are generated using the regtool.

reggen ← uses 85% 1e

The reggen tool processes the IP Hjson file which defines CSRs and countermeasures.

JTAG access port ← part of 85% 1e

JTAG access port is one of the interfaces for which CSR test suites must be added.

CSR-transition coverage metric ← depends on 93% 1e

The metric is defined by observing transitions in CSRs, so it relies on the CSR concept.

RISC-V ISA part of → 92% 1e

CSRs are control and status registers that are part of the RISC-V ISA.

LINKED ENTITIES

3 links

ProcessorFuzz USES Extracted graph relationship

CSR-transition coverage metric DEPENDS_ON Extracted graph relationship

ProcessorFuzz: Guiding Processor Fuzzing using Control and Status Registers MENTIONS Extracted graph relationship

CITATIONS

10 sources

10 citations — click to expand

[1] The RISC-V ISA defines CSRs (Control and Status Register) and special instructions to access them, and the mutation-based CT framework currently focuses on the base RV32I ISA without yet covering CSRs. Mutation-based Compliance Testing for RISC-V

[2] Future work for the mutation-based CT framework includes considering CSRs and additional RISC-V extensions by leveraging existing mutation classes and producing a minimized test-suite that still kills all mutants. Mutation-based Compliance Testing for RISC-V

[3] Virtual memory support requires setting up the CSRs to activate virtual memory support along with appropriate page tables in memory, motivating automated CSR coverage for MMU testing. Mutation-based Compliance Testing for RISC-V

[4] In the Ibex verification flow, ISS models can simulate traps due to exceptions but cannot model traps due to external stimulus; the RISCV-DV handshaking mechanism (signature address 0x8ffffffc) is used to verify that the core correctly enters the proper interrupt handler or Debug Mode and updates any CSRs correctly. Verification — Ibex Documentation

[5] Because the ISS trace log will not contain execution information in the debug ROM or interrupt handler code, the Ibex modified trace-log comparison checks only the final values contained in every register at the end of the test. Verification — Ibex Documentation

[6] ProcessorFuzz guides the fuzzer with a novel CSR-transition coverage metric, because CSRs are in charge of controlling and holding the state of the processor and CSR transitions indicate a new processor state. New Processor Fuzzing Mechanism (Semiconductor Engineering coverage of ProcessorFuzz, arXiv:2209.01789)

[7] ProcessorFuzz is agnostic to the HDL and does not require any instrumentation in the processor design, so it supports a wide range of RTL designs written in different hardware languages. New Processor Fuzzing Mechanism (Semiconductor Engineering coverage of ProcessorFuzz, arXiv:2209.01789)

[8] On Rocket, BOOM, and BlackParrot, ProcessorFuzz triggered ground-truth bugs 1.23× faster on average than DIFUZZRTL, exposed 8 new bugs across the three RISC-V cores and 1 new bug in a reference model, and all nine bugs were confirmed by the developers of the corresponding projects. New Processor Fuzzing Mechanism (Semiconductor Engineering coverage of ProcessorFuzz, arXiv:2209.01789)

[9] The public-context entry 'CSRE4SOC (CSR evaluation for software companies)' uses CSR to mean Corporate Social Responsibility and is not the subject of this article. CSRE4SOC (CSR evaluation for software companies)

[10] The public-context entry 'CSRS: Code Search with Relevance Matching and Semantic Matching' uses CSR(S) for a code-search model and is not the subject of this article. CSRS: Code Search with Relevance Matching and Semantic Matching