STING

Tool

STING is a Synopsys bare-metal functional verification tool for RISC-V processor and SoC implementations. It generates portable, self-checking constrained-random and directed stimulus, including C++-based random streams and ASM-style directed tests, and is used as part of hybrid RISC-V verification flows spanning simulation, emulation, FPGA prototyping, and silicon.

First seen 5/25/2026

Last seen 5/26/2026

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Overview

STING is a bare-metal functional verification tool for RISC-V designs. It generates constrained-random and directed tests for RISC-V processor verification, with stimulus intended to run across simulation, ZeBu emulation, HAPS FPGA prototyping, and silicon. The generated programs are described as architecturally self-checking, which helps simplify debug in verification flows. [C1]

STING is positioned for RISC-V verification because the modular RISC-V ISA and its optional extensions increase verification complexity. Evidence from the source emphasizes that comprehensive RISC-V verification typically requires multiple stimulus techniques rather than either random or directed testing alone. [C2]

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NEIGHBORHOOD

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RELATIONSHIPS

17 connections

Portable Stimulus implements → 97% 3e

STING generates portable stimulus that runs across simulation, emulation, prototyping, and silicon.

Bare-Metal Test Generation implements → 99% 2e

STING is explicitly described as a bare-metal functional verification tool generating bare-metal tests.

Self-Checking Tests implements → 97% 2e

STING-generated tests are architecturally self-checking, simplifying debugging.

constrained-random test generation implements → 99% 2e

STING is a bare-metal generator that produces constrained-random test streams for RISC-V verification.

VCS ← uses 95% 2e

VCS executes STING-generated random tests as part of the verification flow.

ZeBu ← uses 95% 2e

STING-generated portable tests are executed on ZeBu emulation platform.

HAPS ← uses 95% 2e

STING-generated portable tests are executed on HAPS FPGA prototyping platform.

Hybrid Verification Methodology ← uses 97% 2e

The hybrid methodology uses STING for constrained-random test generation.

Hypervisor Extensions evaluates → 93% 1e

STING is particularly effective at stressing hypervisor extensions.

fence.i Instruction evaluates → 92% 1e

STING has exposed mishandling of the fence.i instruction in practice.

Floating-Point NaN evaluates → 91% 1e

STING has exposed floating-point NaN quirks during verification.

Cache Coherence Conflicts evaluates → 91% 1e

STING has exposed cache coherence conflicts during verification runs.

Page Table Walk evaluates → 93% 1e

STING has exposed deadlocks in page-table walks.

Stimulus Graph uses → 96% 1e

STING uses stimulus graphs to enable user control of scheduling of random and directed tests.

Privilege-Mode Transitions evaluates → 93% 1e

STING is particularly effective at stressing privilege levels where traditional flows may miss bugs.

Memory Protection evaluates → 93% 1e

STING stresses memory protection, an area where traditional flows may miss bugs.

CSR evaluates → 93% 1e

STING stresses CSRs as part of its verification capability.

LINKED ENTITIES

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Constrained-Random Testing GENERATES Extracted graph relationship

Directed Testing GENERATES Extracted graph relationship

Stimulus Graphs USES Extracted graph relationship

Synopsys DEVELOPED_BY Extracted graph relationship

RISC-V ISA TARGETS Extracted graph relationship

Hybrid Verification Methodology SUPPORTS Extracted graph relationship

CITATIONS

11 sources

11 citations — click to expand

[1] C1: STING is a bare-metal functional verification tool for RISC-V that generates constrained-random and directed tests, with portable self-checking stimulus across simulation, emulation, FPGA prototypes, and silicon. source

[2] C2: RISC-V verification complexity is increased by the ISA's modular design and optional extensions, and comprehensive coverage typically requires more than one stimulus technique. source

[3] C3: STING produces C++-based random streams and ASM-style directed tests, and includes a framework for directed test development. source

[4] C4: STING uses stimulus graphs to control scheduling of generated random and directed tests. source

[5] C5: A combined strategy uses constrained-random stimulus for breadth and directed tests for precision in RISC-V verification. source

[6] C6: STING is effective at stressing privilege levels, memory protection, CSRs, and hypervisor extensions, and has exposed issues including page-table-walk deadlocks, fence.i mishandling, floating-point NaN quirks, and cache-coherence conflicts. source

[7] C7: STING stimulus can be reused across VCS simulation, ZeBu emulation, HAPS FPGA prototyping, and silicon. source

[8] C8: Portability of tests across verification platforms supports shift-left verification because tests from RTL bring-up remain useful later in validation and silicon. source

[9] C9: A hybrid flow begins with constrained-random sweeps using STING, then uses coverage analysis and targeted directed tests to close gaps. source

[10] C10: Random stimulus with STING helps uncover unexpected behavior and can contribute to faster coverage closure in a hybrid verification approach. source

[11] C11: Self-checking tests, lock-step comparison, logged seeds, and directed reruns improve debug efficiency and reproducibility across regression cycles. source