STING
ToolSTING is a Synopsys bare-metal, software-driven test generator for RISC-V processor and SoC verification. It produces portable, self-checking constrained-random and directed stimulus that can be reused across simulation, emulation, FPGA prototyping, and silicon, and it is used as part of a hybrid RISC-V verification methodology alongside ImperasDV and ImperasTS.
First seen 5/25/2026
Last seen 9/30/2026
Evidence 6 chunks
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Overview
STING is a bare-metal functional verification tool for RISC-V designs, developed for processor and SoC implementation verification. It generates constrained-random and directed tests whose stimulus is intended to run across simulation, ZeBu emulation, HAPS FPGA prototyping, and silicon. The generated programs are architecturally self-checking, which simplifies debugging in verification flows. [C1]
STING is positioned for RISC-V verification because the modular RISC-V ISA and its optional extensions increase verification complexity. The source material emphasizes that comprehensive RISC-V verification typically requires multiple stimulus techniques rather than either random or directed testing alone. [C2]
NEIGHBORHOOD
1 nodes · 0 edgesgraph · STING · depth=1
RELATIONSHIPS
17 connectionsSTING generates portable stimulus that runs across simulation, emulation, prototyping, and silicon.
STING is explicitly described as a bare-metal functional verification tool generating bare-metal tests.
STING-generated tests are architecturally self-checking, simplifying debugging.
STING is a bare-metal generator that produces constrained-random test streams for RISC-V verification.
VCS executes STING-generated random tests as part of the verification flow.
STING-generated portable tests are executed on ZeBu emulation platform.
STING-generated portable tests are executed on HAPS FPGA prototyping platform.
The hybrid methodology uses STING for constrained-random test generation.
STING is particularly effective at stressing hypervisor extensions.
STING has exposed mishandling of the fence.i instruction in practice.
STING has exposed floating-point NaN quirks during verification.
STING has exposed cache coherence conflicts during verification runs.
STING has exposed deadlocks in page-table walks.
STING uses stimulus graphs to enable user control of scheduling of random and directed tests.
STING is particularly effective at stressing privilege levels where traditional flows may miss bugs.
STING stresses memory protection, an area where traditional flows may miss bugs.
STING stresses CSRs as part of its verification capability.
LINKED ENTITIES
7 linksImperasDV integrates_with Evidence pairs STING with ImperasDV, which provides a golden reference model used for lock-step comparison alongside STING's self-checking tests.
ImperasTS complements Evidence describes a hybrid flow combining STING constrained-random stimulus with ImperasTS directed suites for coverage closure.
ImperasFC integrates_with Evidence describes ImperasFC functional coverage being used together with STING in a hybrid coverage-closure flow.
Verdi integrates_with Evidence identifies Verdi as the debug platform used to view coverage and debug results from STING-driven verification flows.
VCS executes_on Evidence names VCS as the simulation platform that executes STING-generated stimulus and replays failing cases deterministically.
ZeBu executes_on Evidence identifies ZeBu emulation as one of the execution targets for STING-generated portable stimulus.
HAPS executes_on Evidence identifies HAPS FPGA prototyping as one of the execution targets for STING-generated portable stimulus.
CITATIONS
11 sources11 citations — click to expand
[1] STING is a bare-metal functional verification tool for RISC-V designs that generates constrained-random and directed tests, with stimulus portable across simulation, emulation, FPGA prototyping, and silicon. RISC-V Test Generation: Random, Directed & Coverage
[2] Comprehensive RISC-V verification typically requires multiple stimulus techniques rather than either random or directed testing alone. RISC-V Test Generation: Random, Directed & Coverage
[3] STING produces C++-based random streams and ASM-style directed tests, built on a lightweight kernel, libraries, and device drivers, and includes a programming framework for developing directed tests. RISC-V Test Generation: Random, Directed & Coverage
[4] STING uses stimulus graphs to enable user control of the scheduling of both random and directed tests generated. RISC-V Test Generation: Random, Directed & Coverage
[5] STING is particularly effective at stressing privilege levels, memory protection, CSRs, and hypervisor extensions. RISC-V Test Generation: Random, Directed & Coverage
[6] STING has exposed issues such as deadlocks in page-table walks, mishandling of the RISC-V fence.i instruction, floating-point NaN quirks, and cache coherence conflicts. RISC-V Test Generation: Random, Directed & Coverage
[7] STING-generated programs are portable across simulation (VCS), emulation (ZeBu), FPGA prototypes (HAPS), and silicon. RISC-V Test Generation: Random, Directed & Coverage
[8] STING's portability enables a shift-left methodology in which tests developed during RTL bring-up remain valuable through later validation stages and silicon. RISC-V Test Generation: Random, Directed & Coverage
[9] A hybrid flow combines constrained-random sweeps using STING with ImperasFC functional coverage analysis and directed ImperasTS suites for coverage closure, with results merged in Verdi and failing cases replayed deterministically in VCS. RISC-V Test Generation: Random, Directed & Coverage
[10] Random stimulus with STING can accelerate coverage closure by uncovering unexpected behaviors, while directed tests improve convergence by targeting known coverage gaps in Sv39/Sv48 page table walks, MMU, PMP, and vector extensions. RISC-V Test Generation: Random, Directed & Coverage
[11] STING-generated tests are self-checking; the methodology pairs them with lock-step comparison against an ImperasDV reference model, and uses logged seeds and directed reruns for reproducibility across regression cycles. RISC-V Test Generation: Random, Directed & Coverage