Bare-Metal Test Generation

Concept

Bare-metal test generation is a RISC-V verification approach centered on generating portable, software-driven tests that can stress processor and SoC behavior across simulation, emulation, FPGA prototyping, and silicon. In the provided evidence, the concept is illustrated primarily through STING, which generates constrained-random and directed bare-metal tests, and through complementary directed suites, coverage analysis, debug, and lock-step comparison flows.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 2 chunks

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Bare-Metal Test Generation

Overview

Bare-metal test generation is used in RISC-V processor verification to create software-driven stimulus that exercises architectural and system behavior directly on verification targets. The provided evidence describes this approach through STING, a bare-metal functional verification tool for RISC-V that generates constrained-random and directed tests. These tests are intended to be portable across simulation, emulation, FPGA prototypes, and silicon, and are self-checking to simplify debugging [STING bare-metal generator].

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RELATIONSHIPS

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STING ← implements 99% 2e

STING is explicitly described as a bare-metal functional verification tool generating bare-metal tests.

LINKED ENTITIES

8 links

RISC-V applies_to The evidence describes bare-metal test generation in the context of RISC-V processor verification and identifies STING as a RISC-V bare-metal generator.

STING implements STING is explicitly described as a bare-metal functional verification tool and a bare-metal, software-driven generator for RISC-V constrained-random and directed tests.

constrained-random test generation uses_technique The evidence identifies constrained-random test generation as a starting point for RISC-V design verification and states that STING generates constrained-random tests.

ImperasDV supports_reference_comparison ImperasDV is described as integrating fast RISC-V reference models and enabling lock-step comparison against a golden reference model at instruction retirement.

VCS executes_tests The evidence states that VCS executes STING-generated random tests and ImperasTS directed suites.

Verdi supports_debug_and_coverage Verdi is described as a debug and analysis platform used for waveforms, mismatch tracking, and functional coverage reporting.

Coverage Closure supports The evidence describes coverage closure as a goal of verification and says VCS executes STING-generated random tests and ImperasTS directed suites to accelerate coverage closure.

Shift-Left Verification enables The evidence states that portable stimulus enables tests to start in simulation and be reused in emulation, prototyping, and silicon, reducing late-stage risk.

CITATIONS

20 sources

20 citations — click to expand

[1] RISC-V verification complexity source

[2] random and directed strategy source

[3] random-alone gaps source

[4] STING bare-metal generator source

[5] STING architecture source

[6] portable stimulus source

[7] shift-left verification source

[8] reported STING findings source

[9] PMP definition source

[10] Sv39 Sv48 definition source

[11] NaN definition source

[12] cache-coherence definition source

[13] coverage closure source

[14] functional stimulus coverage source

[15] ImperasTS closure source

[16] lock-step comparison source

[17] VCS role source

[18] Verdi role source

[19] ZeBu role source

[20] HAPS role source