Constrained Random Test Generation
ConceptConstrained random test generation is a stimuli-generation technique for simulation-based hardware verification that combines randomized test creation with design-specific constraints. Constraints (typically written manually) keep tests valid and bias them toward interesting, hard-to-reach design logic. Its efficiency can degrade as functional coverage saturates, motivating learning-guided extensions such as coverage-directed test selection and novelty-driven verification, as well as hardware-accelerated implementations that pre-process constraints and synthesize constrained random generators in hardware.
First seen 5/26/2026
Last seen 7/7/2026
Evidence 21 chunks
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Constrained Random Test Generation
Overview
Constrained random test generation is one of the most widely adopted methods for generating stimuli for simulation-based hardware verification. It combines randomized test creation with design-specific constraints that keep tests valid and bias generation toward interesting, hard-to-reach, or still-untested design logic. [C1]
NEIGHBORHOOD
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9 connectionsRISC-V DV leverages constrained-random specifications for test generation.
The hybrid methodology combines constrained-random stimulus for breadth with directed suites for precision.
STING is a bare-metal generator that produces constrained-random test streams for RISC-V verification.
The UVM environment uses constrained-random test generation to stimulate the design.
The paper uses constrained-random test generation to verify the VPU.
RISCV-DV generates RISC-V instruction streams based on constrained-random descriptions.
The paper mentions constrained-random test generation as used by RISCV-DV.
TL-Test can generate constrained random test cases quickly for cache verification.
Constrained random test generation is used for generating stimuli in simulation-based verification.
LINKED ENTITIES
3 linksCoverage-Directed Test Selection extends The cited arXiv paper explicitly introduces coverage-directed test selection as a direct response to inefficiency of plain constrained random testing late in verification.
Novelty-Driven Verification complements The hybrid intelligent testing paper combines coverage-directed test selection with novelty-driven verification; both target the inefficiency of constrained random testing.
Functional Coverage related Constrained random testing's main limitation is diminishing returns with respect to functional coverage as verification progresses.
CITATIONS
12 sources12 citations — click to expand
[1] Constrained random test generation is one of the most widely adopted methods for generating stimuli for simulation-based hardware verification, combining randomized tests with design-specific constraints (typically written manually) that keep tests valid and bias them toward interesting, hard-to-reach, yet-untested logic. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
[2] As verification progresses, most constrained random tests yield little to no effect on functional coverage. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
[3] If stimulus generation consumes significantly less resources than simulation, then a better approach involves randomly generating a large number of tests, selecting the most effective subset, and only simulating that subset. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
[4] Constrained value selection in randomized test benches falls into two broad types: selection of control bits (typically Boolean) and selection of data words (e.g., address range or alignment constraints), with data-word constraints suffering combinatorial blow-up under Boolean encoding (e.g., 64 Boolean variables per 64-bit word). Hardware accelerated constrained random test
[5] In real industrial test benches (ARM AMBA, IBM CoreConnect, PCI Bus), constraints involving more than two variables were never required; range constraints and two-variable relations dominate, and an ILP-based software pre-processing step computes the solution region that a synthesized hardware constrained random generator (LFSR-based pseudo-random source plus constraint-specific circuitry) uses to produce valuations with non-zero probability for every satisfying assignment. Hardware accelerated constrained random test
[6] TL-Test is a Unit Level Verification Framework for cache systems that supports the Tilelink protocol and cache coherence checking, quickly generates constrained random test cases, supports converting real cache access traces into testbenches, and can detect injected bugs such as a Grant Data shift by 8 bits at address 0x4000. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
[7] In a RISC-V-based system with a V²PRO vector co-processor, random vector instruction generation enforces RAW-hazard avoidance, chaining/deadlock avoidance, and chain-sequence finalization constraints, with result comparison against a RISC-V twin to flag verification failures. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
[8] PATARA imports processor and instruction descriptions from XML, randomly initializes register-file content, supports stacked test cases (chained modification operations with restoring operations in reverse order), and defines RISC-V ADD with SUB as its reverse counterpart. Hybrid Intelligent Testing in Simulation-Based Verification
[9] RISC-V-targeted constrained random generators include the Torture Test generator (Scala, randomized test-sequences), RISCV-DV (Google, SystemVerilog + UVM), and a fuzzing-based ELF-generating approach; these do not support the compliance testing format, making mutation-based compliance testing complementary. Hybrid Intelligent Testing in Simulation-Based Verification
[10] EPEX is an equivalent-program-execution verification approach using a formal ISA model and an SMT solver to replace each instruction with an equivalent sequence, presented as complementary to constrained random and coverage-guided generation. Hybrid Intelligent Testing in Simulation-Based Verification
[11] Coverage-directed test selection uses supervised learning from coverage feedback to perform automatic constraint extraction and test selection, reducing manual constraint writing, prioritizing effective tests, reducing resource consumption, and accelerating coverage closure on a large industrial design. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
[12] Hybrid intelligent testing combines coverage-directed test selection with novelty-driven verification to address each method's individual limitations. Hybrid Intelligent Testing in Simulation-Based Verification