Constrained Random Test Generation

Concept

Constrained random test generation is a widely used method for producing stimuli in simulation-based hardware verification. It combines randomized test creation with design-specific constraints that keep tests valid and bias them toward interesting, hard-to-reach, or yet-untested logic. As verification progresses, generated tests often stop contributing to functional coverage, which has motivated selection-based and learning-based extensions such as coverage-directed test selection. The approach is also used in practice by verification infrastructures such as TL-Test for cache verification and by online self-testing flows for RISC-V-based systems with vector co-processors.

First seen 5/26/2026

Last seen 6/6/2026

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Constrained Random Test Generation

Overview

Constrained random test generation is a method for creating stimuli for simulation-based verification by combining randomized test creation with constraints that steer generation toward interesting, hard-to-reach, or still-untested design logic. In the cited simulation-based verification literature, it is described as one of the most widely adopted approaches for generating stimuli. [C1]

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RELATIONSHIPS

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riscv-dv ← implements 96% 3e

RISCV-DV implements constrained-random test generation for RISC-V designs.

UVM environment ← uses 97% 2e

The UVM environment uses constrained-random test generation to stimulate the design.

Functional Verification of a RISC-V Vector Accelerator ← uses 97% 2e

The paper uses constrained-random test generation to verify the VPU.

Hybrid Verification Methodology ← uses 98% 2e

The hybrid methodology combines constrained-random stimulus for breadth with directed suites for precision.

STING ← implements 99% 2e

STING is a bare-metal generator that produces constrained-random test streams for RISC-V verification.

TL-Test ← implements 97% 1e

TL-Test can generate constrained random test cases quickly for cache verification.

Stimuli Generation uses → 100% 1e

Constrained random test generation is used for generating stimuli in simulation-based verification.

riscv-dv ← uses 100% 1e

RISC-V DV generates instruction streams based on constrained-random descriptions.

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TL-Test IMPLEMENTS Extracted graph relationship

CITATIONS

11 sources

11 citations — click to expand

[1] Constrained random test generation is one of the most widely adopted methods for generating stimuli for simulation-based verification. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification

[2] Randomness leads to test diversity while constraints (typically written manually) bias random tests toward interesting, hard-to-reach, and yet-untested logic. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification

[3] As verification progresses, most constrained random tests yield little to no effect on functional coverage. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification

[4] If stimuli generation consumes significantly less resources than simulation, a better approach is to randomly generate many tests, select the most effective subset, and simulate only that subset. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification

[5] TL-Test is a Unit Level Verification Framework for cache systems that supports the Tilelink protocol and cache coherence, and can quickly generate constrained random testcases; it also supports converting real cache access traces into testbenches for trace-driven cache verification. XiangShan ASPLOS'25 Tutorial: Function Verification (TL-Test section)

[6] In the RISC-V/V²PRO verification flow, random generation covers operations, operands and addressing parameters, vector lengths, vector-lane assignments, and input data for the co-processor and reference arrays, in order to increase code coverage across repeated tests. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor

[7] For repeatability and performance, the RISC-V/V²PRO random generation was performed offline with a constant seed for coverage evaluation, while the same automatic procedure is also available as a single RISC-V program for post-silicon validation or FPGA-based pre-silicon verification. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor

[8] V²PRO constrained-random generation checks operand addresses to avoid RAW hazards over a window set to pipeline depth, tracks per-lane chaining state to prevent all-lane deadlock, and emits chain-finalizing instructions based on the final chain state to ensure valid sequence completion. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor

[9] After the test sequence is executed on both V²PRO and the RISC-V reference twin, the co-processor's register-file and local-memory contents are copied to external memory by DMA and compared to the RISC-V reference; mismatches cause verification failure with detailed reports. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor

[10] Generating tests and processed data through an online constrained-random process on the RISC-V reduces dependence on communication with an external test unit. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor

[11] Coverage-directed test selection uses supervised learning from coverage feedback to perform automatic constraint extraction and test selection, biasing simulation toward tests likely to increase functional coverage and accelerating coverage closure on a real industrial hardware design. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification