UVM environment
ConceptFirst seen 6/1/2026
Last seen 6/1/2026
Evidence 10 chunks
NEIGHBORHOOD
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18 connectionsThe UVM environment uses RISCV-DV to generate random RISC-V assembly tests for vector instruction testing.
The UVM environment uses SystemVerilog Assertions to improve observability of the design.
The UVM environment implements a functional coverage plan to measure verification completeness.
The UVM environment uses constrained-random test generation to stimulate the design.
The UVM environment performs step-by-step co-simulation of all vector instructions.
The verification environment includes a bare metal test harness as shown in the environment overview.
The UVM environment uses ISA tests to cover instruction formats and parameters per the vector specification.
The UVM environment uses directed tests to cover specific scenarios like different vstart values.
The UVM environment handles memory operation retries as part of OVI protocol handling.
The UVM environment handles masked memory operations, comparing masks with those in Spike.
The UVM environment generates stimulus for the VPU through virtual sequences and agents.
The UVM environment uses random binary generation via RISCV-DV as part of its verification approach.
The UVM environment uses Spike as a reference model for co-simulation of vector instructions.
The UVM environment uses transaction-level modeling for communication between components.
The UVM environment includes a UVM scoreboard to compare VPU results with the reference model.
The UVM environment contains one agent per sub-interface of the OVI.
The UVM environment uses virtual sequences to create interface-specific transactions.
The UVM environment uses UVM events to synchronize sub-interface communication between virtual sequences.