UVM environment

Concept

First seen 6/1/2026

Last seen 9/12/2026

Evidence 15 chunks

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Functional Coverage uses → 97% 3e

A UVM environment incorporates functional-coverage collectors for measuring verification completeness.

Co-simulation uses → 98% 2e

The UVM environment performs step-by-step co-simulation of all vector instructions.

riscv-dv uses → 97% 2e

The UVM environment uses RISCV-DV to generate random RISC-V assembly tests for vector instruction testing.

SystemVerilog Assertions uses → 97% 2e

The UVM environment uses SystemVerilog Assertions to improve observability of the design.

constrained-random test generation uses → 97% 2e

The UVM environment uses constrained-random test generation to stimulate the design.

Instruction Stream Generator uses → 88% 2e

UVM environments use instruction-stream generators to supply stimulus.

ISA Tests uses → 95% 1e

The UVM environment uses ISA tests to cover instruction formats and parameters per the vector specification.

Directed Tests uses → 95% 1e

The UVM environment uses directed tests to cover specific scenarios like different vstart values.

spike uses → 98% 1e

The UVM environment uses Spike as a reference model for co-simulation of vector instructions.

masked memory operation uses → 95% 1e

The UVM environment handles masked memory operations, comparing masks with those in Spike.

Stimulus Generation uses → 95% 1e

The UVM environment generates stimulus for the VPU through virtual sequences and agents.

random binary generation uses → 96% 1e

The UVM environment uses random binary generation via RISCV-DV as part of its verification approach.

Transaction Level Modeling uses → 90% 1e

The UVM environment uses transaction-level modeling for communication between components.

RISC-V Verification IP part of → 95% 1e

RISC-V Verification IP includes UVM components as part of its reusable assets.

riscv-dv ← uses 97% 1e

riscv-dv is built on SystemVerilog/UVM and uses the UVM framework.

Core-V-Verif ← uses 90% 1e

CORE-V-VERIF integrates UVM as the verification environment framework.

Reference Model uses → 93% 1e

UVM environments integrate reference-model interfaces for architectural state comparison.

Assertions and Checkers uses → 90% 1e

UVM environments integrate assertion results as part of the checking infrastructure.

memory operation retry uses → 94% 1e

The UVM environment handles memory operation retries as part of OVI protocol handling.

UVM scoreboard uses → 98% 1e

The UVM environment includes a UVM scoreboard to compare VPU results with the reference model.

UVM agent ← part of 98% 1e

The UVM environment contains one agent per sub-interface of the OVI.

virtual sequence uses → 97% 1e

The UVM environment uses virtual sequences to create interface-specific transactions.

UVM events uses → 97% 1e

The UVM environment uses UVM events to synchronize sub-interface communication between virtual sequences.

bare metal test harness uses → 88% 1e

The verification environment includes a bare metal test harness as shown in the environment overview.