SystemVerilog Assertions

Concept

SystemVerilog Assertions (SVA) were used in a RISC-V vector accelerator verification environment to check Open Vector Interface behavior, improve observability, and detect both VPU design bugs and UVM stimulation problems.

First seen 5/27/2026

Last seen 6/9/2026

Evidence 5 chunks

Wiki v1

WIKI

Overview

SystemVerilog Assertions (SVA) are presented in the evidence as an assertion mechanism used inside a hardware verification environment to check that an interface behaves as expected. In the cited RISC-V vector processor unit (VPU) verification work, the team added SVA specifically to improve observability when result mismatches alone did not identify the cause of an error. [C1]

Use in VPU interface verification

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NEIGHBORHOOD

2 nodes · 1 edges

graph · SystemVerilog Assertions · depth=1

RELATIONSHIPS

4 connections

Functional Verification of a RISC-V Vector Accelerator ← uses 99% 4e

SystemVerilog assertions are used to improve observability and check interface behavior

UVM environment ← uses 97% 2e

The UVM environment uses SystemVerilog Assertions to improve observability of the design.

SymbiYosys ← uses 100% 1e

SymbiYosys verifies properties written using SystemVerilog Assertions.

UVM testbench ← uses 93% 1e

The UVM testbench is complemented with SystemVerilog Assertions for protocol checking.

LINKED ENTITIES

2 links

Functional Verification of a RISC-V Vector Accelerator USES Extracted graph relationship

UVM testbench USES Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] C1: SystemVerilog assertions were added to improve observability when result mismatches did not identify the cause of an error; the environment also used a UVM scoreboard and Spike co-simulation. source

[2] C2: The verification team wrote more than 50 SystemVerilog Assertions to check expected VPU/OVI interface behavior. source

[3] C3: Most asserted properties targeted memory-related sub-interfaces and enforced OVI specification compliance during the project. source

[4] C4: During early UVM testbench development, the assertions helped identify bugs in the VPU and problems in UVM stimulation. source

[5] C5: The bibliography cites Eduard Cerny et al., SVA: The Power of Assertions, Springer International Publishing, 2015. source