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SystemVerilog Assertions

Concept WIKI v1 · 5/27/2026

SystemVerilog Assertions (SVA) were used in a RISC-V vector accelerator verification environment to check Open Vector Interface behavior, improve observability, and detect both VPU design bugs and UVM stimulation problems.

Overview

SystemVerilog Assertions (SVA) are presented in the evidence as an assertion mechanism used inside a hardware verification environment to check that an interface behaves as expected. In the cited RISC-V vector processor unit (VPU) verification work, the team added SVA specifically to improve observability when result mismatches alone did not identify the cause of an error. [C1]

Use in VPU interface verification

A critical verification target in the referenced project was the VPU interface. The team reviewed the Open Vector Interface (OVI) specifications and wrote more than 50 SystemVerilog Assertions to check that the VPU interface behaved as expected. [C2]

Most asserted properties targeted memory-related OVI sub-interfaces and were intended to ensure that the OVI specifications were strictly followed throughout the project. [C3]

Interaction with the UVM testbench

The assertions were used during early UVM testbench development. They helped identify both bugs in the VPU and problems in UVM stimulation. [C4]

The broader verification setup also used a UVM scoreboard that compared VPU results against a reference model, with Spike used for co-simulation. In that context, assertions complemented result checking by improving observability when an instruction-result mismatch was detected but did not directly reveal the cause. [C1]

Practical role

Within the cited verification flow, SVA served as an interface-level checking and debug aid:

  • checking expected OVI behavior;
  • enforcing OVI specification compliance on selected sub-interfaces;
  • improving observability beyond scoreboard mismatches;
  • finding both design-side VPU bugs and verification-side stimulation issues. [C1][C2][C3][C4]

Bibliographic context

The project bibliography cites SVA: The Power of Assertions by Eduard Cerny et al. as a reference for SystemVerilog Assertions. [C5]

LINKED ENTITIES

2 links
Functional Verification of a RISC-V Vector Accelerator USES
UVM testbench USES

CITATIONS

5 sources
5 citations
[1] C1: SystemVerilog assertions were added to improve observability when result mismatches did not identify the cause of an error; the environment also used a UVM scoreboard and Spike co-simulation. source
[2] C2: The verification team wrote more than 50 SystemVerilog Assertions to check expected VPU/OVI interface behavior. source
[3] C3: Most asserted properties targeted memory-related sub-interfaces and enforced OVI specification compliance during the project. source
[4] C4: During early UVM testbench development, the assertions helped identify bugs in the VPU and problems in UVM stimulation. source
[5] C5: The bibliography cites Eduard Cerny et al., SVA: The Power of Assertions, Springer International Publishing, 2015. source