Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core

Paper

First seen 7/10/2026

Last seen 7/10/2026

Evidence 14 chunks

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RELATIONSHIPS

31 connections

Simulation-based Fault Injection ← compares with 90% 2e

The paper compares its backward tracing formal method with simulation-based forward tracing.

Model Checking uses → 100% 2e

The paper uses model checking as its formal verification approach.

Backward Tracing uses → 100% 2e

The paper proposes backward tracing to identify and categorize faults by their effects.

Ibex Core evaluates → 100% 2e

The paper evaluates the SEU reliability of the RISC-V Ibex Core.

Strobe Properties uses → 95% 2e

Strobe properties are developed to identify SEUs causing SDCs by comparing golden and faulty cores.

Architectural Properties uses → 95% 2e

Architectural properties specify RISC-V core behavior to identify SEUs.

Crash Properties uses → 95% 2e

Crash properties are developed to find SEUs that cause crashes.

Hang Properties uses → 90% 2e

Hang properties are developed to identify SEUs causing system hangs.

SystemVerilog assertions uses → 100% 1e

Properties are written as SystemVerilog Assertions for model checking.

Cadence JasperGold FPV uses → 100% 1e

Cadence JasperGold FPV is used to perform model checking at the RTL level.

JasperGold Superlint App uses → 90% 1e

JasperGold Superlint App is used to automatically generate Dead State and Live State properties.

SystemVerilog uses → 95% 1e

AUX code in SystemVerilog is developed to abstract memories.

Triple Modular Redundancy mentions → 90% 1e

Triple Modular Redundancy is suggested as a protection technique for vulnerable bits such as the program counter.

Cone-Of-Influence Analysis uses → 90% 1e

COI analysis is used in model checking to filter irrelevant signals and speed up verification.

memory abstraction uses → 95% 1e

Memory abstraction is used to reduce state space by black-boxing IMEM and DMEM.

Double Event Upset mentions → 90% 1e

Double Event Upsets are mentioned as future work to expand the method.

Fault Tree Analysis mentions → 85% 1e

Fault Tree Analysis is mentioned in the related work as a system reliability evaluation method.

Runtime Verification mentions → 85% 1e

Runtime verification is mentioned as a type of formal verification technique used in related work.

Bing Xue authored by → 100% 1e

The paper is authored by Bing Xue.

XOR-Gate Fault Injection uses → 90% 1e

Faults are injected using XOR gates added to the design.

Fault Controller Module uses → 90% 1e

A fault controller module outputs mask signals to control the XOR gates for fault injection.

AUX SystemVerilog Code uses → 95% 1e

Auxiliary SystemVerilog code is developed to abstract memories and handle communication signals.

Simulation-based Fault Injection mentions → 90% 1e

Simulation-based fault injection is mentioned as the widely used alternative to formal verification.

Random Fault Injection mentions → 90% 1e

Random fault injection is mentioned as a compromise that reduces accuracy and fault coverage.

Mark Zwolinski authored by → 100% 1e

The paper is authored by Mark Zwolinski.

University of Southampton published by → 100% 1e

The authors are affiliated with the University of Southampton.

formal verification uses → 100% 1e

The paper uses formal verification to evaluate hardware reliability.

Fault Coverage mentions → 90% 1e

Fault coverage is mentioned as a metric reduced by random fault injection.

bounded model checking uses → 95% 1e

Bounded Model Checking is used as an alternative to full model checking to handle state explosion.

ISO 26262 mentions → 95% 1e

ISO 26262 mandates simulation-based fault injection for automotive safety applications.

Fault Injection uses → 90% 1e

Fault injection is implemented as part of the SEU identification method.