Directed Tests

Concept

Directed tests are hand- or systematically-targeted verification stimuli that exercise specific scenarios, instructions, or interfaces rather than relying on broad random exploration. In the CHIA RISC-V ISA extension case study, directed tests are auto-generated one minimal program per instruction from `specs/<ext>/instructions.json` and cosimulated against Spike to prove each instruction in isolation. Wider RISC-V verification literature treats directed tests as a necessary but insufficient complement to constrained-random and architectural regression suites.

First seen 5/27/2026

Last seen 7/28/2026

Evidence 9 chunks

Wiki v2

WIKI

Overview

Directed tests are verification stimuli that target specific scenarios, instructions, interfaces, or corner cases rather than producing broad random exploration. In simulation-based functional verification of processors they are typically written (or auto-generated) to exercise a known behavior end-to-end and are checked against a reference model, an assertion set, or expected outputs. Functional verification surveys of RISC-V processors explicitly identify stimulus as "either directed tests or random tests," with directed tests favoring targeted, hand-checked scenarios and random tests favoring broader coverage of input combinations.

Use in the CHIA RISC-V ISA extension case study

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NEIGHBORHOOD

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RELATIONSHIPS

9 connections

CHIA ← uses 98% 2e

CHIA runs directed tests — one program per instruction — differentially against Spike.

Functional Verification of a RISC-V Vector Accelerator ← uses 97% 2e

Directed tests are developed to cover specific edge cases and added to the regression suite.

Verification of a RISC-V system with multiple cores ← uses 100% 2e

Directed tests are used alongside random tests in the verification strategy.

Random Instruction Generation compares with → 85% 1e

Teams must decide which behaviours belong in directed tests versus constrained-random regressions.

run_vext_loop ← uses 93% 1e

run_vext_loop builds and runs directed tests as part of the verification pipeline.

regression suite ← uses 90% 1e

Directed tests are added to the regression suite to cover specific scenarios.

isa_tests ← implements 97% 1e

isa_tests emits one minimal program per instruction, implementing the directed test generation.

UVM environment ← uses 95% 1e

The UVM environment uses directed tests to cover specific scenarios like different vstart values.

Functional Verification ← uses 95% 1e

Functional verification applies directed tests as stimulus inputs to the DUT.

LINKED ENTITIES

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CHIA USES Extracted graph relationship

run_vext_loop USES Extracted graph relationship

isa_tests IMPLEMENTS Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] Directed tests are a formal stage of the CHIA riscv_extensions pipeline that runs after reset and before the base-ISA regression and stress phase. RISC-V ISA Extension Implementation — CHIA main documentation

[2] Directed tests in CHIA are auto-generated one minimal program per instruction from `specs/<ext>/instructions.json`, cross-compiled to an ELF, and yield 100% instruction coverage by construction. RISC-V ISA Extension Implementation — CHIA main documentation

[3] Every directed test in CHIA is judged by running it on the DUT with Spike riding inside the simulator (`CosimNode`), failing at the first architectural disagreement. RISC-V ISA Extension Implementation — CHIA main documentation

[4] The Survey of Verification of RISC-V Processors classifies stimulus as "either directed tests or random tests" within functional verification. Survey of Verification of RISC-V Processors

[5] A multi-core RISC-V verification project used UVM-directed tests for JTAG and DMA alongside architectural tests, and found that riscv-tests plus a few directed tests were necessary but not sufficient, motivating a complement of random tests. Verification of a RISC-V system with multiple cores