ISA Tests

Concept

In the cited RISC-V vector accelerator verification work, ISA tests are a directed instruction-coverage mechanism used to quickly exercise key RISC-V Vector specification 0.7.1 configurations, complementing RISCV-DV random tests and other coverage-oriented verification activities.

First seen 5/27/2026

Last seen 6/1/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

In the available evidence, ISA tests refer to a set of tests developed for instruction coverage of a RISC-V vector accelerator against the RISC-V Vector specification 0.7.1v. The tests were used to quickly exercise key instruction-format configurations, including Vector Length, Single Element Width, rounding modes, and masks. [C1]

Role in verification

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NEIGHBORHOOD

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RELATIONSHIPS

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Functional Verification of a RISC-V Vector Accelerator ← uses 97% 1e

ISA tests are developed for instruction coverage of the 0.7.1 spec

UVM environment ← uses 95% 1e

The UVM environment uses ISA tests to cover instruction formats and parameters per the vector specification.

LINKED ENTITIES

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Functional Verification of a RISC-V Vector Accelerator USES Extracted graph relationship

CITATIONS

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1 citations — click to collapse

[1] ISA tests were developed for instruction coverage of RISC-V Vector specification 0.7.1v formats and key configurations such as Vector Length, Single Element Width, rounding modes, and masks; they were used alongside RISCV-DV random tests and complemented by functional and directed coverage for load/store scenarios. Functional Verification of a RISC-V Vector Accelerator