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ISA Tests

Concept WIKI v1 · 5/27/2026

In the cited RISC-V vector accelerator verification work, ISA tests are a directed instruction-coverage mechanism used to quickly exercise key RISC-V Vector specification 0.7.1 configurations, complementing RISCV-DV random tests and other coverage-oriented verification activities.

Overview

In the available evidence, ISA tests refer to a set of tests developed for instruction coverage of a RISC-V vector accelerator against the RISC-V Vector specification 0.7.1v. The tests were used to quickly exercise key instruction-format configurations, including Vector Length, Single Element Width, rounding modes, and masks. [C1]

Role in verification

The ISA tests were part of a broader verification strategy. They were run in parallel with RISCV-DV random tests, which were used for additional stress testing. The same verification effort also included functional coverage for diverse load and store scenarios and directed regression tests for load retries with different vstart values. [C1]

Covered configuration areas

The evidence explicitly associates the ISA tests with instruction coverage across RISC-V Vector specification 0.7.1v formats and key configurations:

  • Vector Length
  • Single Element Width
  • Rounding Modes
  • Masks

These tests were intended to cover important configurations quickly, while random and directed tests provided complementary stress and scenario coverage. [C1]

Related work

The paper Functional Verification of a RISC-V Vector Accelerator uses ISA tests as part of its verification methodology for a RISC-V vector processing unit.

LINKED ENTITIES

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Functional Verification of a RISC-V Vector Accelerator USES

CITATIONS

1 sources
1 citations
[1] ISA tests were developed for instruction coverage of RISC-V Vector specification 0.7.1v formats and key configurations such as Vector Length, Single Element Width, rounding modes, and masks; they were used alongside RISCV-DV random tests and complemented by functional and directed coverage for load/store scenarios. Functional Verification of a RISC-V Vector Accelerator