Verification of a RISC-V system with multiple cores
PaperFirst seen 6/18/2026
Last seen 6/18/2026
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34 connectionsA modified version of Spike ISS is used as the reference model for co-simulation.
AXI interfaces are used in the CPU-Subsystem for memory and peripheral connections.
The paper introduces a standalone UVM environment at the core-level called Core-UVM.
The paper introduces a CPU-Subsystem UVM environment at the system level.
Regression testing is used to detect buggy updates in the design.
The verification approach employs co-simulation with the Spike ISS to check design correctness.
The paper relies on Spike as a reference model for validating RISC-V designs.
The paper presents a verification strategy based on the Universal Verification Methodology (UVM).
Random binary generation is used via riscv-dv for test generation.
Directed tests are used alongside random tests in the verification strategy.
UVM directed tests are used for verifying the DMA interface.
riscv-dv is used to generate random binaries for testing.
Random interrupt generation is employed to test interrupt handling in the design.
riscv-tests is used as a source of directed tests.
Vector memory instructions are generated with changing SEW and vector length values.
Atomic instruction stress tests are included to focus on randomized atomic instructions.
Register randomization for key registers is added as a feature to riscv-dv.
UVM directed tests are used for verifying the JTAG interface.
Issues in exception and trap handlers were fixed in riscv-dv for accurate test generation.
Oscar Palomar is listed as first author of the paper.
The paper is developed as part of the Barcelona Zettascale Lab project.
Roberto Ignacio Genovese is listed as a co-author of the paper.
Iván Díaz Ortega is listed as a co-author of the paper.
Albert Aguilera is listed as a co-author of the paper.
Abdul Rauf is listed as a co-author of the paper, affiliated with ARM.
The majority of authors are affiliated with Barcelona Supercomputing Center.
Functional coverage is a key challenge addressed in the paper.
SVA assertions are implemented in selected module interfaces.
A scoreboard is used to detect mismatches and signal test failures.
SystemVerilog DPI calls are implemented to enable interaction between Spike and the UVM environment.
AXI Master VIP is used to verify the DMA bridge in the subsystem.
Spike is modified to support bootrom preloading from an .elf file for flexible environment usage.
RISC-V compliance tests are used as directed tests in the verification flow.
Full support for RVV 1.0.0 vector instructions is added to riscv-dv for testing.