Atomic Instructions Stress Tests
ConceptAtomic instructions stress tests are a category of randomized verification stimuli used in RISC-V system verification, focusing on the generation of randomized atomic instructions to exercise a design's atomic memory operations.
First seen 6/18/2026
Last seen 6/18/2026
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Overview
Atomic instructions stress tests are a class of randomized stimuli used in the functional verification of RISC-V based systems. They are characterized by their focus on generating randomized atomic instructions in order to stress a design's atomic memory operation handling logic and surrounding microarchitecture.
Role in Verification Flows
NEIGHBORHOOD
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2 connectionsAtomic instruction stress tests are included to focus on randomized atomic instructions.
riscv-dv is used to generate atomic instruction stress tests.
CITATIONS
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[1] Atomic instructions stress tests focus on generating randomized atomic instructions. Verification of a RISC-V system with multiple cores
[2] Atomic instructions stress tests are used as part of the test suite for verifying a RISC-V system with multiple cores, alongside basic scalar tests, basic vector tests, riscv-isa-tests, riscv-arch-tests, internal RVV ISA tests, and UVM directed tests for JTAG and DMA interfaces. Verification of a RISC-V system with multiple cores
[3] The bulk of tests used in the RISC-V multi-core verification flow come from random generation, and the project relies on tools such as riscv-dv to complement the initial regression suite with random tests. Verification of a RISC-V system with multiple cores