riscv-dv

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riscv-dv is an open-source RISC-V instruction stream generator (ISG) used to produce constrained-random instruction streams for hardware design verification of RISC-V processor implementations. Originally hosted at google/riscv-dv, it is now maintained under the chipsalliance organization on GitHub as a Python-based project widely used alongside golden reference models in step-and-compare verification flows.

First seen 9/24/2026

Last seen 9/24/2026

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riscv-dv

Overview

riscv-dv is an open-source, Python-based tool that generates random instruction streams for the verification of RISC-V processor implementations. It is commonly categorized as a constrained-random Instruction Stream Generator (ISG), meaning it produces randomized but ISA-legal test programs that exercise a target RISC-V design under test (DUT) together with a golden reference model in a step-and-compare verification flow.

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graph · riscv-dv · depth=1

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Constrained-random instruction stream generation (ISG) implements → 93% 1e

The Google riscv-dv project functions as a constrained-random instruction stream generator for RISC-V verification.

Instruction Stream Generator (ISG) implements → 91% 1e

riscv-dv is explicitly described as a DV-ISG, i.e., an instruction stream generator used in RISC-V processor verification.

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Constrained-random instruction stream generation (ISG) IMPLEMENTS Extracted graph relationship

Instruction Stream Generator (ISG) IMPLEMENTS Extracted graph relationship

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[1] riscv-dv is an open-source Python project that generates random instruction streams for RISC-V processor verification, hosted at chipsalliance/riscv-dv with ~1357 stars and ~399 forks, last updated 2026-09-21. chipsalliance/riscv-dv

[2] riscv-dv was originally published as the Google RISC-V DV-ISG open-source project under google/riscv-dv and is referenced by Imperas Software as a constrained-random Instruction Stream Generator (ISG) used alongside the RISC-V International Compliance suite and directed tests in step-and-compare verification flows against a golden RISC-V reference model. Imperas Leading RISC-V CPU Reference Model for Hardware Design Verification Selected by Mellanox