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riscv-dv

CodeArtifact WIKI v1 · 9/24/2026

riscv-dv is an open-source RISC-V instruction stream generator (ISG) used to produce constrained-random instruction streams for hardware design verification of RISC-V processor implementations. Originally hosted at google/riscv-dv, it is now maintained under the chipsalliance organization on GitHub as a Python-based project widely used alongside golden reference models in step-and-compare verification flows.

riscv-dv

Overview

riscv-dv is an open-source, Python-based tool that generates random instruction streams for the verification of RISC-V processor implementations. It is commonly categorized as a constrained-random Instruction Stream Generator (ISG), meaning it produces randomized but ISA-legal test programs that exercise a target RISC-V design under test (DUT) together with a golden reference model in a step-and-compare verification flow.

The project is hosted on GitHub and is currently maintained under the chipsalliance organization. According to the GitHub repository metadata for chipsalliance/riscv-dv:

  • Language: Python
  • Stars: ~1,357
  • Forks: ~399
  • Description: "Random instruction generator for RISC-V processor verification"
  • Last updated: 2026-09-21

URL: https://github.com/chipsalliance/riscv-dv

Origin and Project Lineage

riscv-dv was originally published as the Google RISC-V DV-ISG open-source project under google/riscv-dv. It was developed to supply the RISC-V hardware verification community with a constrained-random stimulus generator that complements other stimulus types such as the RISC-V International compliance suite and directed tests. Subsequent maintenance has been carried out under the ChipsAlliance organization, which hosts the current canonical repository chipsalliance/riscv-dv.

Role in RISC-V Hardware Verification

In a typical RISC-V processor design verification (DV) environment, riscv-dv provides one of several stimulus categories used to validate RTL against a golden reference model. A standard verification flow combines:

  • The RISC-V International Compliance Suite for architectural compliance testing,
  • Directed tests for handcrafted corner cases, and
  • Constrained-random Instruction Stream Generator (ISG) tests, of which riscv-dv is a representative open-source example.

Imperas Software has publicly described using this taxonomy when discussing verification flows for RISC-V processors (see the public statement referenced in the Citations section). In such a flow, the RTL and a RISC-V reference model (e.g., from Imperas) are run side-by-side, and riscv-dv-generated programs are executed on both, with step-and-compare analysis used to flag divergences either interactively or in automated regression tests for continuous integration.

Techniques Implemented

riscv-dv implements two closely related techniques in the verification domain:

  • Instruction Stream Generator (ISG) – generating sequences of instructions usable as stimulus for processor verification.
  • Constrained-random instruction stream generation (ISG) – producing instruction streams that are randomized within the constraints of the RISC-V ISA, enabling broader coverage than directed testing while remaining ISA-legal.

Use in Industrial Flows

Because RISC-V is an open ISA that permits many configurations, options, and custom instruction extensions, verification teams frequently pair riscv-dv-style random stimulus with reference models that are available in source form and can be extended with custom instructions. The reference model is typically encapsulated in a UVM environment to form a complete SystemVerilog DV flow, after which constrained-random streams from riscv-dv can be replayed against both the reference and the DUT.

Project Status

The repository at chipsalliance/riscv-dv is actively maintained (most recent recorded update: 2026-09-21) and continues to be referenced by external verification vendors and academic work as a representative open-source RISC-V ISG.

References

LINKED ENTITIES

2 links
Constrained-random instruction stream generation (ISG) IMPLEMENTS
Instruction Stream Generator (ISG) IMPLEMENTS

CITATIONS

2 sources
2 citations
[1] riscv-dv is an open-source Python project that generates random instruction streams for RISC-V processor verification, hosted at chipsalliance/riscv-dv with ~1357 stars and ~399 forks, last updated 2026-09-21. chipsalliance/riscv-dv
[2] riscv-dv was originally published as the Google RISC-V DV-ISG open-source project under google/riscv-dv and is referenced by Imperas Software as a constrained-random Instruction Stream Generator (ISG) used alongside the RISC-V International Compliance suite and directed tests in step-and-compare verification flows against a golden RISC-V reference model. Imperas Leading RISC-V CPU Reference Model for Hardware Design Verification Selected by Mellanox