Instruction Stream Generator (ISG)

Technique

A constrained-random stimulus-generation technique used in RISC-V hardware design verification to produce randomized instruction streams that exercise the RTL in step-and-compare flows against a golden reference model.

First seen 9/24/2026

Last seen 9/24/2026

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Instruction Stream Generator (ISG)

Overview

An Instruction Stream Generator (ISG) is a stimulus-generation technique employed in hardware design verification (DV) flows for processors. In the context of RISC-V verification, an ISG produces randomized but architecturally constrained sequences of instructions that serve as inputs to the design under test. These randomized instruction streams are one of several stimulus categories used to validate that a processor implementation conforms to the ISA and to its specified microarchitectural behavior.

Role in Verification Flows

ISG-based tests are typically deployed alongside other stimulus types in a comprehensive RISC-V processor verification plan. Common companion stimuli include:

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RELATIONSHIPS

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riscv-dv ← implements 91% 1e

riscv-dv is explicitly described as a DV-ISG, i.e., an instruction stream generator used in RISC-V processor verification.

Constrained-random instruction stream generation (ISG) ← extends 84% 1e

Constrained-random ISG is presented as a specific form of ISG testing, indicating it is a specialization of the broader ISG technique.

LINKED ENTITIES

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riscv-dv IMPLEMENTS Extracted graph relationship

Constrained-random instruction stream generation (ISG) EXTENDS Extracted graph relationship

CITATIONS

3 sources

3 citations — click to collapse

[1] ISG is used as a constrained-random stimulus type in RISC-V processor verification plans, alongside the RISC-V International Association Compliance suite and directed tests. Imperas Leading RISC-V CPU Reference Model for Hardware Design Verification Selected by Mellanox

[2] ISG-generated tests are applied in step-and-compare flows where a RTL design is run side-by-side with a golden reference model such as the Imperas RISC-V model, encapsulated in a UVM/SystemVerilog environment, either interactively or in automated regression tests for continuous integration. Imperas Leading RISC-V CPU Reference Model for Hardware Design Verification Selected by Mellanox

[3] The Google RISC-V DV-ISG project at https://github.com/google/riscv-dv is cited as an open-source example of a constrained-random Instruction Stream Generator used in RISC-V hardware verification. Imperas Leading RISC-V CPU Reference Model for Hardware Design Verification Selected by Mellanox