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Atomic Instructions Stress Tests

Concept WIKI v1 · 6/18/2026

Atomic instructions stress tests are a category of randomized verification stimuli used in RISC-V system verification, focusing on the generation of randomized atomic instructions to exercise a design's atomic memory operations.

Overview

Atomic instructions stress tests are a class of randomized stimuli used in the functional verification of RISC-V based systems. They are characterized by their focus on generating randomized atomic instructions in order to stress a design's atomic memory operation handling logic and surrounding microarchitecture.

Role in Verification Flows

In the verification of a RISC-V system with multiple cores (described by Genovese et al. at the 2025 RISC-V Summit Europe), atomic instructions stress tests form one of several complementary test categories used alongside other directed and randomized suites. They are listed among the test types used by the project, together with:

  • Basic scalar tests and basic vector tests that target scalar and vector instruction and memory operation behavior, with the vector variant emphasizing vector instructions and memory operations.
  • Regression suites drawn from external sources, including the riscv-isa-tests, the riscv-arch-tests (formerly compliance), and internal RVV ISA tests.
  • UVM directed tests verifying the JTAG and DMA interfaces.

The project reports that the bulk of its tests come from random generation, and that atomic instructions stress tests are part of this randomized stimulus strategy. The project's reference model is a modified Spike ISS (extended with SystemVerilog DPI calls and a core_type configuration flag) that is co-simulated with the UVM environment.

Generation Methodology

The evidence indicates that atomic instructions stress tests are produced through randomized generation rather than hand-written sequences. The associated project also relied on riscv-dv as a random instruction-sequence generator tool, and used targeted selection of random tests that had previously uncovered difficult bugs in order to improve regression quality.

Tools and Infrastructure

  • riscv-dv: a random test-program generator that produces randomized RISC-V instruction sequences, used to complement the initial regression set with random tests including atomic-instruction-focused variants.
  • riscv-tests: contributed directed and architectural tests to the regression baseline.
  • Spike: the golden reference model, modified to provide DPI integration and implementation-specific modeling.

See Also

LINKED ENTITIES

2 links
Verification of a RISC-V system with multiple cores USES
RISCV-DV USES

CITATIONS

3 sources
3 citations
[1] Atomic instructions stress tests focus on generating randomized atomic instructions. Verification of a RISC-V system with multiple cores
[2] Atomic instructions stress tests are used as part of the test suite for verifying a RISC-V system with multiple cores, alongside basic scalar tests, basic vector tests, riscv-isa-tests, riscv-arch-tests, internal RVV ISA tests, and UVM directed tests for JTAG and DMA interfaces. Verification of a RISC-V system with multiple cores
[3] The bulk of tests used in the RISC-V multi-core verification flow come from random generation, and the project relies on tools such as riscv-dv to complement the initial regression suite with random tests. Verification of a RISC-V system with multiple cores