Bootrom Preloading
ConceptA modification to the Spike RISC-V instruction set simulator that allows a boot ROM image to be preloaded from an .elf file, enabling Spike to be used as a flexible reference model across different verification environments and SoC designs.
First seen 6/18/2026
Last seen 6/18/2026
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Overview
Bootrom preloading is a capability added to the RISC-V Spike instruction set simulator (ISS) that allows the simulator to be initialized with a boot ROM image loaded directly from an .elf file. The feature was introduced as part of adapting Spike for use as a reference model in the UVM-based verification of a multi-core RISC-V system.
Motivation
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2 connectionsSpike is modified to support bootrom preloading from an .elf file for flexible environment usage.
Spike is modified to support bootrom preloading from an .elf file.
CITATIONS
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[1] Spike was modified to allow the preloading of a bootrom from an .elf file. Verification of a RISC-V system with multiple cores
[2] The bootrom preloading modification gives Spike the flexibility to be used with different environments and designs. Verification of a RISC-V system with multiple cores
[3] Bootrom preloading is part of a broader set of Spike adaptations used as a UVM reference model, including a core_type configuration flag, DPI calls to step the simulator per committed instruction, DPI calls to force values, interrupt toggling, and silent TLB walks. Verification of a RISC-V system with multiple cores
[4] The verification flow that uses bootrom preloading combines riscv-isa-tests, riscv-arch-tests, internal RVV tests, UVM directed tests for JTAG and DMA, and randomized riscv-dv-generated tests, and supports multi-binary runs. Verification of a RISC-V system with multiple cores