AXI interface

Concept

The AXI (Advanced eXtensible Interface) on-chip bus protocol is used in three verification/emulation contexts described in the evidence: (1) in the Condominium FPGA-based co-emulation framework, where hardened Zynq AXI interfaces and DPI-C-issued AXI transactions connect the PS host to PL-Shell CSRs and FIFOs for DUT control and memory access; (2) in the Zynq-Parrot / ZP Cosim emulation of BlackParrot on the Ultra96v2 board, where high-performance master and slave Zynq AXI interfaces connect the PS to DRAM, the FPGA shell, and BlackParrot's slave port; and (3) in the RISC-V multi-core system-level UVM verification environment, where AXI master/slave VIPs and a Pulp AXI crossbar exercise memory, peripheral, and DMA traffic on the CPU subsystem.

First seen 6/18/2026

Last seen 7/11/2026

Evidence 8 chunks

Wiki v3

WIKI

AXI interface

Overview

AXI (Advanced eXtensible Interface) is an on-chip bus protocol used to connect processor subsystems to memory, peripherals, and DMA infrastructure. The evidence describes three distinct uses of AXI:

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NEIGHBORHOOD

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RELATIONSHIPS

5 connections

Verification of a RISC-V system with multiple cores ← uses 100% 2e

AXI interfaces are used in the CPU-Subsystem for memory and peripheral connections.

Condominium ← uses 97% 2e

Condominium uses hardened AXI interfaces on Zynq for PS-PL communication

ZP Cosim ← uses 92% 2e

ZP Cosim uses AXI interfaces for communication between PS and PL in the FPGA shell

Zynq-Parrot ← uses 97% 2e

Zynq-Parrot wraps processors with a flexible AXI interface

CPU-Subsystem UVM environment ← uses 100% 1e

The CPU-Subsystem environment uses AXI interfaces for memory and peripheral bus connections.

LINKED ENTITIES

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ZP Cosim USES Extracted graph relationship

Zynq-Parrot USES Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] Zynq FPGA boards couple hardened ARM cores (PS) with a programmable fabric (PL) and the PS communicates with the PL via hardened AXI interfaces; PS master ports are GP AXI and PS client ports are HP AXI allowing PL to directly access PS DRAM controllers. Condominium thesis chapter (UW digital library)

[2] Condominium's host-side APIs initiate AXI read/write requests to MMIO locations in the PL-Shell; on the Zynq PS they are translated to AXI over hardened interfaces, and on Verilator they use DPI-C to issue AXI transactions directly at the PL-Shell ports. Condominium thesis chapter (UW digital library)

[3] Condominium uses C++ coroutines to service each AXI transaction in parallel because many commercial simulators disallow native multi-threading, providing parallelism and deadlock avoidance for parallel AXI transactions and design simulation. Condominium thesis chapter (UW digital library)

[4] Zynq-Parrot is a customizable FPGA shell that presents a flexible AXI wrapper around accelerators and soft processors such as BlackParrot, hosted on Zynq boards including the Ultra96v2 with Zynq UltraScale+ MPSoC ZU3EG A484 (quad-core Cortex-A53, NEON, FP, 2 GB LPDDR4). Zynq-Parrot thesis chapter (UW digital library)

[5] Zynq-Parrot uses 2 of 6 high-performance slave AXI interfaces in 32-bit configuration for DRAM communication (m00), and 2 high-performance master AXI interfaces in 32-bit configuration for the FPGA shell (s01) and the slave port of BlackParrot (s00). Zynq-Parrot thesis chapter (UW digital library)

[6] The Zynq-Parrot PS control program (ps.cpp, C++ or Python) memory-maps the AXI interface address space to user memory and uses it to flash the bitstream (PYNQ), reset BlackParrot, initialize DRAM pointers and shell CSRs, load RISC-V binaries, configure BlackParrot registers, handle environment calls, and read/write FIFOs and registers in the FPGA shell. Zynq-Parrot thesis chapter (UW digital library)

[7] The Zynq-Parrot FPGA shell wraps a unicore BlackParrot configuration and exposes a parameterized number of synchronous FIFOs and general-purpose registers that the PS reads and writes via the s01 AXI master port. Zynq-Parrot thesis chapter (UW digital library)

[8] ZP Cosim supports simulating BlackParrot in Verilator and Synopsys VCS and emulating ZP Cosim on the FPGA via Zynq-Parrot, with Verilator generating functional models for the ZP Cosim hardware infrastructure (synthesizable on the FPGA) and BlackParrot, linked with the control program and Dramajo cosimulation libraries. Zynq-Parrot thesis chapter (UW digital library)