AXI interface

Overview

AXI (Advanced eXtensible Interface) is an on-chip bus protocol used to connect processor subsystems to memory, peripherals, and DMA infrastructure. The evidence describes three distinct uses of AXI:

1. In the Condominium FPGA-based co-emulation framework, AXI provides the bridge between the Zynq Processing System (PS) host software and the Programmable Logic (PL) DUT, both via the Zynq's hardened AXI interfaces and via DPI-C transactions injected into software RTL simulation.
2. In the Zynq-Parrot / ZP Cosim emulation of BlackParrot on the Avnet Ultra96v2 board, AXI is the on-chip bus exposed by the Zynq UltraScale+ MPSoC PS and is used in 32-bit configuration over the hardened high-performance master/slave ports to reach DRAM, the FPGA shell, and the BlackParrot slave port.
3. In the RISC-V multi-core system-level verification environment (2025 RISC-V Summit Europe paper Verification of a RISC-V system with multiple cores), AXI is the on-chip interconnect protocol exposed by the CPU subsystem and is modelled in the UVM testbench using VIPs from the Pulp project.

Condominium: AXI between PS and PL-Shell

Zynq-based architecture

Zynq FPGA boards couple hardened ARM cores (the PS) with programmable fabric (the PL). The PS communicates with the PL over hardened AXI interfaces:

• The PS's master ports are general-purpose (GP) AXI ports covering a small address space.
• The PS's client (slave) ports are higher-performance (HP) AXI ports that allow the PL to directly access dedicated DDR controllers for PS DRAM, bypassing the ARM L2 cache-coherence system and avoiding PS-Linux-stack interference.

Condominium decomposes the prototyped system into these functional domains by mapping the subsystem DUT to the PL fabric while leveraging PS software for memory access, peripheral modelling, and emulation configuration. Compared with PCIe tunnels, hardened Zynq AXI interfaces provide direct and low-latency access to design peripherals such as host DRAM, supporting high-performance emulation of designs that require low-latency on-chip memory access.

Identical host code over AXI on FPGA or simulation

Condominium aims to provide reproducible emulation with identical host controller code on both FPGA and software RTL simulator targets. To interface with the PL-Shell, target-specific APIs initiate AXI read and write requests to MMIO locations in the PL-Shell:

• On the Zynq PS (FPGA target): the APIs perform MMIO reads and writes that are translated to AXI transactions over the Zynq's hardened AXI interfaces.
• On software RTL simulators (e.g., Verilator): the same APIs leverage DPI-C interfaces to issue AXI transactions directly at the PL-Shell ports.

Because many commercial simulators disallow native multi-threading, Condominium uses C++ coroutines to service each AXI transaction in parallel and to avoid deadlock while handling parallel AXI transactions and design simulation.

C++ host-side AXI helpers

Example host-side helper functions operating on the PS's MMIO-mapped GP0 region (shown in Figure 3.2) include:

cpp int axi_read(int addr) { while (!pl->read(SHELL_FIFO_Y_CNT)) ; // wait for response in FIFO Y return *((int *)(gp0_ptr + addr)); }

void axi_write(int addr, int data) { *((int *)(gp0_ptr + addr)) = data; }

cpp // Write 0xcafe to FIFO X and read response from FIFO Y pl->write(SHELL_FIFO_X, 0xcafe); int val2 = pl->read(SHELL_FIFO_Y);

init() maps the PS-side MMIO region (gp0_ptr = mmap(GP0_PADDR)) and allocates the PL DRAM buffer (dram_ptr = cma_alloc(PL_DRAM_SIZE)), so that subsequent axi_read/axi_write calls become MMIO transactions translated into AXI on the Zynq or into DPI-C-driven AXI on Verilator.

Zynq-Parrot / ZP Cosim: AXI between PS and BlackParrot on Ultra96v2

Zynq-Parrot is a customizable FPGA shell built around the open-source BlackParrot processor and was originally conceived as a flexible AXI wrapper around accelerators and soft processors for Zynq-7000 boards. In the thesis evidence, the discussion focuses on evaluating BlackParrot on the Avnet Ultra96v2 board, which uses the Xilinx Zynq UltraScale+ MPSoC ZU3EG A484 — a quad-core ARM Cortex-A53 PS with NEON SIMD, single/double-precision floating point, and 2 GB of LPDDR4.

AXI interfaces used between the PS and the PL

Zynq-Parrot communicates with the PL through the hardened PS-PL interfaces on the Zynq UltraScale+ MPSoC, all in 32-bit configuration:

• 2 of 6 high-performance slave AXI interfaces are used for DRAM communication (port m00 in Figure 3.3), giving the PL direct access to PS DRAM.
• 2 high-performance master AXI interfaces are used for:
  • Communication with the FPGA shell (port s01 in Figure 3.3), over which the PS reads/writes the parameterized synchronous FIFOs and general-purpose registers hosted in the shell.
  • Communication with the slave port of BlackParrot (port s00 in Figure 3.3), over which the PS loads RISC-V program binaries and writes BlackParrot configuration registers.

The bus that carries AXI Full traffic to DRAM is labelled "AXI Full to DRAM" in Figure 3.3.

The PS-side control program

The PS runs a control program (ps.cpp, in C++ or Python) that memory-maps the AXI address space into user memory and uses it to:

• Flash the system bitstream on the PL using PYNQ APIs.
• Reset BlackParrot hardware, and initialize DRAM pointers and other configuration registers in the shell (PL) by writing to CSRs in the shell.
• Load RISC-V-compliant program binaries and write configuration registers in the address space of BlackParrot.
• Process and respond to environment calls, and interpret termination signals from BlackParrot.
• Read and write FIFOs and registers in the FPGA shell for auxiliary information such as profiling data.

FPGA shell behaviour over AXI

The FPGA shell wraps a unicore BlackParrot configuration and hosts a parameterized number of synchronous FIFOs and general-purpose registers that can be read and written by the PS via the s01 AXI master port. This is the same AXI-based PS↔PL-Shell control model used in Condominium, but instantiated for BlackParrot on Ultra96v2.

RISC-V multi-core verification: AXI in the UVM testbench

In the system-level UVM environment described in Verification of a RISC-V system with multiple cores, AXI is the on-chip bus used to connect the CPU subsystem to memory, peripherals, and DMA infrastructure.

AXI endpoints on the CPU subsystem

The CPU-subsystem DUT exposes AXI endpoints alongside JTAG and interrupt signals:

• AXI – Slave Memories that emulate main memory, SRAM, and bootrom, modelled with the axi-mem component from the Pulp project.
• AXI – Master VIP to support verification of the DMA bridge and to exchange and access different design blocks of the RTL through DMA.
• AXI crossbar from the Pulp project, used to connect both an SRAM and the UART to the peripheral bus.

Testbench composition

These AXI components are integrated into the testbench alongside:

• PLIC / CLINT UVM agents that generate external, timer, and software interrupts at the subsystem level and verify their handling by the RTL.
• A UART model attached to the peripheral bus via the Pulp AXI crossbar.
• A JTAG VIP and debug module.

Role in the verification flow

• The AXI slave memories back the bootrom loaded from an .elf file by the Spike-based reference model.
• The AXI master VIP drives DMA traffic into the subsystem's slave port to verify the DMA bridge.
• The AXI crossbar multiplexes peripheral traffic between the SRAM and UART, providing realistic peripheral-bus behaviour to the DUT.

The testbench also reuses core-uvm (in passive mode), JTAG VIP, and the Spike DPI reference model alongside the AXI components.

Related concepts

• Condominium uses AXI as the PS↔PL transport, both via hardened Zynq AXI and via DPI-C transactions in software simulation. Condominium also builds upon the BaseJump STL library to provide generic and open bridges to commonly available AXI and UART interfaces.
• Zynq-Parrot uses hardened Zynq UltraScale+ high-performance master/slave AXI interfaces (in 32-bit configuration) to connect the PS control program to DRAM, the FPGA shell, and the BlackParrot slave port; it is the emulation substrate for ZP Cosim running on Verilator, Synopsys VCS, and the FPGA.
• The CPU-Subsystem UVM environment for the RISC-V multi-core design integrates AXI slave memories, an AXI master VIP, and a Pulp AXI crossbar into the system-level testbench.