Regression Testing

Concept

Regression testing, in the provided TestRIG context, is represented as a library of saved instruction-trace counterexamples that can be replayed to quickly check previously observed failures. TestRIG’s trace import/export, shrinking, and simplification mechanisms support producing maintainable regression tests from discovered counterexamples.

First seen 5/27/2026

Last seen 5/27/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

In the TestRIG evidence, regression testing is described operationally as collecting a library of instruction-trace tests that can be used to quickly check all previous counterexamples. These regression tests are derived from instruction traces rather than hand-written assertion tests, and the evidence states that they do not require maintenance in the way hand-written tests with assertions do.

Test artifact format

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RELATIONSHIPS

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TestRIG ← uses 90% 1e

TestRIG supports regression testing via sequence import/export functionality.

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TestRIG USES Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] Regression tests are collected as a library of instruction traces used to quickly check previous counterexamples. Randomized Testing of RISC-V CPUs using Direct

[2] Instruction traces can be converted to and from a human-readable format and read or written individually or in bulk from a directory. Randomized Testing of RISC-V CPUs using Direct

[3] Trace-based regression tests are contrasted with hand-written tests with assertions and are described as not requiring maintenance. Randomized Testing of RISC-V CPUs using Direct

[4] In model-based testing, shrinking or simplification is safe to try because any changed trace that still diverges is kept. Randomized Testing of RISC-V CPUs using Direct

[5] Smart shrinking can eliminate irrelevant instructions and transform a counterexample sequence, including propagating output registers to future input operands. Randomized Testing of RISC-V CPUs using Direct