Verdi

Tool

Verdi is a debug and analysis platform used in RISC-V verification flows for waveform analysis, mismatch tracking, centralized debug, and functional coverage reporting. In the provided evidence, it is used with SystemVerilog coverage generated by ImperasFC/SC, VCS simulation, and ImperasDV reference-model comparison to support iterative coverage closure.

First seen 5/25/2026

Last seen 5/26/2026

Evidence 3 chunks

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Overview

Verdi is described as a debug and analysis platform used for waveforms, mismatch tracking, and functional coverage reporting in RISC-V verification environments.

In the cited RISC-V verification flow, Verdi acts as a standard coverage reporting and debug environment for conventional SystemVerilog functional coverage. Because ImperasFC-generated functional coverage is SystemVerilog, the resulting coverage data can be viewed in Verdi.

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NEIGHBORHOOD

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RELATIONSHIPS

5 connections

ImperasFC uses → 95% 2e

ImperasFC results are merged and viewed in Verdi for unified coverage analysis.

ImperasSC uses → 95% 2e

ImperasSC results are merged and viewed in Verdi for unified coverage reporting.

Functional Coverage evaluates → 96% 2e

Verdi is used for functional coverage reporting and analysis, viewing coverage results from ImperasFC.

Hybrid Verification Methodology ← uses 95% 2e

The hybrid methodology uses Verdi for merging coverage results and debug analysis.

VCS ← compares with 88% 1e

Verdi and VCS are used together in the hybrid flow; results are merged in Verdi and failing cases are replayed in VCS.

LINKED ENTITIES

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CITATIONS

6 sources

6 citations — click to expand

[1] Verdi is a debug and analysis platform used for waveforms, mismatch tracking, and functional coverage reporting. source

[2] ImperasFC and ImperasSC auto-generate SystemVerilog coverage models for RISC-V ISA features, provide coverage metrics, and integrate with Verdi. source

[3] Functional coverage generated by ImperasFC can be viewed in a standard coverage reporting tool such as Verdi because it is conventional SystemVerilog. source

[4] A hybrid RISC-V coverage-closure flow uses constrained-random sweeps, ImperasFC functional coverage analysis, Verdi result merging, and deterministic replay of failing cases in VCS. source

[5] In an example RISC-V verification flow, constrained-random programs run in simulators such as VCS while Verdi provides centralized debug. source

[6] ImperasDV enables lock-step comparison against a reference model at instruction retirement in the described verification flow. source