Overview

Verdi is described as a debug and analysis platform used for waveforms, mismatch tracking, and functional coverage reporting in RISC-V verification environments.

In the cited RISC-V verification flow, Verdi acts as a standard coverage reporting and debug environment for conventional SystemVerilog functional coverage. Because ImperasFC-generated functional coverage is SystemVerilog, the resulting coverage data can be viewed in Verdi.

Role in RISC-V coverage closure

A typical coverage-closure workflow described in the evidence begins with constrained-random sweeps, followed by functional coverage analysis using ImperasFC. ImperasFC generates SystemVerilog coverage models directly from the ISA specification, and the resulting coverage can be reviewed in Verdi.

The same flow also supports shift-left verification. Coverage analysis can begin before RTL using ImperasSC. After RTL becomes available, coverage gaps are highlighted and closed, results are merged in Verdi, and failing cases are replayed deterministically in VCS. This creates an iterative loop that combines broad random stimulus with targeted closure.

Integration context

Verdi appears in the provided evidence as part of a broader RISC-V verification toolbox that includes simulation, reference models, directed and constrained-random tests, and hardware-assisted platforms.

In one example, constrained-random programs are executed in simulators such as VCS while Verdi provides centralized debug. ImperasDV enables lock-step comparison against a reference model at instruction retirement, and the same stimulus can later be reused in ZeBu emulation or HAPS prototyping.

Related coverage tooling

ImperasFC and ImperasSC are described as functional and stimulus coverage tools that auto-generate SystemVerilog coverage models for RISC-V ISA features. The evidence states that these tools provide detailed coverage metrics and integrate with Verdi.