Coverage Closure

Concept

Coverage Closure is the hardware verification process of reaching sufficient functional and code coverage to justify confidence that relevant design behaviours have been tested. The provided evidence emphasizes feedback-driven simulation techniques—supervised test selection, multi-armed-bandit scheduling, feedback-based sequence-duration control, and recurrent-neural-network constraint tuning—that use coverage feedback to prioritize stimuli and accelerate functional coverage convergence.

First seen 5/25/2026

Last seen 6/3/2026

Evidence 8 chunks

Wiki v2

WIKI

Definition

Coverage Closure is the process of achieving sufficient functional and code coverage to provide confidence that all relevant design behaviours have been tested. [Coverage closure definition]

In simulation-based processor verification, stimuli are generated and applied to a design while achieved functional coverage is monitored as an indicator of verification completeness. [Simulation-based coverage monitoring]

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RELATIONSHIPS

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Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification ← evaluates 100% 3e

The paper demonstrates that its method can accelerate coverage closure on a large industrial hardware design.

Hybrid Verification Methodology ← implements 97% 2e

The hybrid flow is designed to achieve coverage closure by combining random and directed stimulus.

Functional Coverage uses → 93% 2e

Coverage closure is achieved by analyzing functional coverage gaps and targeting them with directed tests.

Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification ← uses 100% 2e

The paper demonstrates that coverage-directed test selection can accelerate coverage closure.

Automation of Processor Verification Using Recurrent Neural Networks ← mentions 100% 1e

The paper reports that coverage closure is achieved much sooner with the proposed technique.

LINKED ENTITIES

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Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification EVALUATES Extracted graph relationship

CITATIONS

11 sources

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[1] Coverage closure is the process of achieving sufficient functional and code coverage to provide confidence that all relevant design behaviours have been tested. RISC-V test generation: random, directed, coverage

[2] Simulation-based processor verification applies generated stimuli and monitors achieved functional coverage to determine verification completeness. Automation of Processor Verification Using Recurrent Neural Networks

[3] Constrained-random generation is widely used, but tests can repeatedly exercise the same design logic; manual constraints are used to bias generation, and late-stage random tests often add little functional coverage. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification

[4] Coverage-directed test selection uses supervised learning from coverage feedback to select and prioritize tests likely to increase functional coverage, reducing manual constraint writing, resource consumption, and closure time. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification

[5] In the MAB formulation for UVM verification, test sequences are treated as arms, rewards are based on coverage performance, and sequence choice balances exploration and exploitation. UVM-based verification of RISC-V superscalar processors

[6] Functional coverpoints describe architecturally interesting aspects of the DUT, and achieved coverage measures test-plan effectiveness and exploration of general and corner cases. UVM-based verification of RISC-V superscalar processors

[7] RISC-V MAB case studies reached higher functional coverage goals without manual intervention and achieved 1.5× to 2× simulation-time savings compared with random scheduling. UVM-based verification of RISC-V superscalar processors

[8] A UCB1 MAB experiment with 40 virtual sequences reached the same coverage as 5,000 random trials faster, averaging 1,988 MAB trials and 60% savings; random coverage ranged from 82% to 91%. UVM-based verification of RISC-V superscalar processors

[9] With a fixed sequence set, UCB1 does not improve the sequence set’s quality; it identifies the set’s coverage potential more quickly than traditional approaches. UVM-based verification of RISC-V superscalar processors

[10] A feedback-based technique adjusts sequence simulation duration using incremental functional-coverage contribution and reports approximately 70% simulation-time savings. UVM-based verification of RISC-V superscalar processors

[11] A recurrent-neural-network technique dynamically alters pseudorandom-generator constraints using coverage feedback, achieving coverage closure sooner and isolating a small set of high-coverage regression stimuli. Automation of Processor Verification Using Recurrent Neural Networks