Self-Checking Tests

Concept

Self-checking tests are used in RISC-V verification flows to automatically validate test outcomes, often by comparing results against a reference model. In the provided evidence, ImperasTS suites self-check and compare against a reference model, while STING generates portable self-checking programs for simulation, emulation, FPGA prototyping, and silicon.

First seen 5/25/2026

Last seen 5/26/2026

Evidence 3 chunks

Wiki v1

WIKI

Overview

Self-checking tests are tests or programs that validate their own execution results rather than relying solely on external inspection. In the cited RISC-V verification flow, ImperasTS suites are described as self-checking and as automatically comparing results against a reference model, which helps uncover subtle design issues and accelerate coverage closure. [C1]

Role in RISC-V Verification

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NEIGHBORHOOD

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RELATIONSHIPS

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STING ← implements 97% 2e

STING-generated tests are architecturally self-checking, simplifying debugging.

LINKED ENTITIES

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STING generates The evidence defines STING as a bare-metal functional verification tool that generates portable, self-checking programs for RISC-V.

Lock-Step Compare used_with The evidence states that architecturally self-checking tests are combined with lock-step compare in ImperasDV to identify mismatches immediately.

ImperasDV integrated_with The evidence says self-checking tests are combined with lock-step compare in ImperasDV and that TS-ISA tests are included with ImperasDV licences.

Coverage Closure supports The evidence states that self-checking ImperasTS suites help accelerate coverage closure and that the hybrid methodology delivers faster coverage closure.

CITATIONS

8 sources

8 citations — click to expand

[1] ImperasTS suites self-check and automatically compare results against a reference model, helping uncover subtle design issues and accelerate coverage closure. source

[2] STING generates portable, self-checking RISC-V programs that run across simulation, emulation, FPGA prototypes, and silicon while supporting constrained-random and directed stimulus. source

[3] Combining architecturally self-checking tests with lock-step compare in ImperasDV enables immediate mismatch identification and simplifies root-cause analysis. source

[4] Lock-step compare runs RTL and a golden reference model in parallel and compares results at instruction retirement for early bug detection. source

[5] Portable tests can be used across simulation, emulation, FPGA prototyping, and silicon, enabling shift-left validation from RTL bring-up through later stages. source

[6] The hybrid methodology improves coverage closure by combining random stimulus that uncovers unexpected behavior with directed ImperasTS suites for precise coverage convergence. source

[7] Logged seeds and directed reruns support reproducibility across regression cycles. source

[8] The evidence identifies TS-ISA, TS-VECT, and TS-MMU/PMP/ePMP as ImperasTS suite categories for architectural validation, vector extensions, and memory-management or protection features. source